Patents by Inventor Gerhard Grassl

Gerhard Grassl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4803622
    Abstract: An I/O bus sequencer for providing a data path between an execution Unit (EU-10), a register file (14) and devices connected to a bus (28). A programmable logic array (PLA-18) stores a program which controls a service table (20). The service table includes a plurality of entries divided into fields. One of the fields when decoded instructs the PLA as to what kind of operation the bus sequencer is to perform. Line selection (priority) logic (22) connected to I/O request lines (30) and to the service table (20) determines which service table entry the PLA is to use. A bus interface connected to the I/O bus ports (26) and to the PLA (18) routes data between the I/O bus ports (26) and the register file (14), entries of which are controlled by use of register sets. The service table fields include register set descriptors for storing the status of register set buffers.
    Type: Grant
    Filed: May 7, 1987
    Date of Patent: February 7, 1989
    Assignee: Intel Corporation
    Inventors: William L. Bain, Jr., Robert C. Bedichek, George W. Cox, Gerhard Grassl, Craig B. Peterson, Justin R. Rattner, Gurbir Singh, Gurbir Singh, John L. Wipfli
  • Patent number: 4517672
    Abstract: A function check of a programmable logic array is performed in which input lines, product term lines and ground lines are combined into an AND plane and output lines, product term lines and ground lines are combined into an OR plane. The aim is a simple method of function check which permits any potentially-existing fault to be detected. The check is achieved by generating, with a test data generator, bit patterns and applying the same to the input lines, and, through the use of a shift register, successively sensitizing the product term lines either individually or in groups, i.e. disconnecting the same from ground potential. The bit patterns occurring at the output lines are supplied to a test data evaluator. The area of use is in logic circuitry of data processing technology.
    Type: Grant
    Filed: July 23, 1982
    Date of Patent: May 14, 1985
    Assignee: Siemens Aktiengesellschaft
    Inventors: Hans-Joerg Pfleiderer, Gerhard Grassl
  • Patent number: 4250568
    Abstract: A semiconductor storage circuit has a plurality of storage elements which are provided with storage capacitors and which are grouped in rows and columns and integrated on a doped semiconductor body. The storage elements which form a row are provided with a common first drive line and the storage elements which form a column are provided with a second common drive line. The first drive lines are formed from strip-like electrically conductive layers which are separated by an insulating layer from the surface of the semiconductor body and the second drive lines consist of buried lines which extend within the semiconductor body and are oppositely doped with respect to the body. The insulating layer is designed to be thinner within the intersection zones of the drive lines so that in these zones insulating layer capacitors are formed which possess outer electrodes composed of parts of the first drive lines and which represent storage capacitors of the storage elements.
    Type: Grant
    Filed: November 28, 1979
    Date of Patent: February 10, 1981
    Assignee: Siemens Aktiengesellschaft
    Inventor: Gerhard Grassl