Abstract: In a circuit arrangement including a plurality of multi-position data switches and a memory connected for storing, in respective addressable memory locations, representations of the positions of the data switches, each data switch is a multi-digit coding switch having an actuating input and a plurality of code outputs at which appear a set of signals representative of the setting of the switch upon appearance of a signal at its actuating input, and the arrangement further includes a multiplex signal generator having a plurality of clock outputs each connected to the actuating input of a respective coding switch, the generator being arranged to produce a sequence of pulse signals and to deliver each pulse signal of the sequence to a respective clock output, and a bus bar composed of a plurality of conductors equal in number to the number of code outputs of each coding switch, with each conductor being connected between the memory and a respective coding output of each coding switch so that the appearance of a