Patents by Inventor Gerhard Knoblinger
Gerhard Knoblinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220122756Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.Type: ApplicationFiled: December 30, 2021Publication date: April 21, 2022Inventors: Andreas WOLTER, Thorsten MEYER, Gerhard KNOBLINGER
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Patent number: 11250981Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.Type: GrantFiled: August 13, 2020Date of Patent: February 15, 2022Assignee: Intel CorporationInventors: Andreas Wolter, Thorsten Meyer, Gerhard Knoblinger
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Publication number: 20200381161Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.Type: ApplicationFiled: August 13, 2020Publication date: December 3, 2020Inventors: Andreas WOLTER, Thorsten MEYER, Gerhard KNOBLINGER
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Patent number: 10784033Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.Type: GrantFiled: March 27, 2019Date of Patent: September 22, 2020Assignee: Intel IP CorporationInventors: Andreas Wolter, Thorsten Meyer, Gerhard Knoblinger
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Publication number: 20190221349Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.Type: ApplicationFiled: March 27, 2019Publication date: July 18, 2019Inventors: Andreas Wolter, Thorsten Meyer, Gerhard Knoblinger
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Patent number: 10290412Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.Type: GrantFiled: June 25, 2015Date of Patent: May 14, 2019Assignee: Intel IP CorporationInventors: Andreas Wolter, Thorsten Meyer, Gerhard Knoblinger
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Publication number: 20160379747Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.Type: ApplicationFiled: June 25, 2015Publication date: December 29, 2016Inventors: Andreas Wolter, Thorsten Meyer, Gerhard Knoblinger
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Patent number: 9490834Abstract: A digital-to-analog converter circuit including a plurality of digital-to-analog converter cells is provided. A first digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide alternatingly a first voltage and a second voltage to a first electrode of a capacitive element of the first digital-to-analog converter cell based on a digital input signal during a predefined time interval. A second digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide a third voltage to a first electrode of a capacitive element of the second digital-to-analog converter cell during the predefined time interval.Type: GrantFiled: February 19, 2016Date of Patent: November 8, 2016Assignee: Intel IP CorporationInventors: Stephan Leuschner, Michael Fulde, Daniel Sira, Gerhard Knoblinger
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Publication number: 20160285470Abstract: A digital-to-analog converter circuit including a plurality of digital-to-analog converter cells is provided. A first digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide alternatingly a first voltage and a second voltage to a first electrode of a capacitive element of the first digital-to-analog converter cell based on a digital input signal during a predefined time interval. A second digital-to-analog converter cell of the plurality of digital-to-analog converter cells includes a cell control module configured to provide a third voltage to a first electrode of a capacitive element of the second digital-to-analog converter cell during the predefined time interval.Type: ApplicationFiled: February 19, 2016Publication date: September 29, 2016Inventors: Stephan Leuschner, Michael Fulde, Daniel Sira, Gerhard Knoblinger
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Patent number: 8877576Abstract: An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first area and a second area. The first area is stress engineered to provide enhanced mobility in a first channel that has a first width. The second area is stress engineered to provide enhanced mobility in a second channel that has a second width. The first channel and the second channel provide a combined current that is greater than a single current provided via a single channel having a single width that is substantially equal to the sum of the first width and the second width.Type: GrantFiled: August 23, 2007Date of Patent: November 4, 2014Assignee: Infineon Technologies AGInventors: Gerhard Knoblinger, Franz Kuttner
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Patent number: 8492796Abstract: An electronic circuit on a semiconductor substrate having isolated multiple field effect transistor circuit blocks is disclosed. In some embodiment, an apparatus includes a substrate, a first semiconductor circuit formed above the substrate, a second semiconductor circuit formed above the substrate, and a MuGFET device overlying the substrate and electrically coupled to the first semiconductor circuit and the second semiconductor circuit, wherein the MuGFET device provides a signal path between the first semiconductor circuit and the second semiconductor circuit in response to an input signal.Type: GrantFiled: March 13, 2007Date of Patent: July 23, 2013Assignee: Infineon Technologies AGInventor: Gerhard Knoblinger
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Patent number: 8450156Abstract: In a method for producing a thyristor, first and second connection regions are formed on or above a substrate; the first connection region is doped with dopant atoms of a first conductivity type and the second connection region is doped with dopant atoms of a second conductivity type; first and second body regions are formed between the connection regions, wherein the first body region is formed between the first connection region and second body region, and the second body region is formed between the first body region and second connection region; the first body region is doped with dopant atoms of the second conductivity type and the second body region is doped with dopant atoms of the first conductivity type, wherein the dopant atoms are in each case introduced into the respective body region using a Vt implantation method; a gate region is formed on or above the body regions.Type: GrantFiled: May 29, 2012Date of Patent: May 28, 2013Assignee: Infineon Technologies AGInventors: Harald Gossner, Thomas Schulz, Christian Russ, Gerhard Knoblinger
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Patent number: 8368144Abstract: An electronic circuit on a semiconductor substrate having isolated multiple gate field effect transistor circuit blocks is disclosed. In some embodiments, an electronic circuit has a substrate having a buried oxide insulating region. A MuGFET device may be formed above the buried oxide region and coupled to a first source of reference potential. A semiconductor device may be formed above the substrate and coupled to a second source of reference potential. A coupling network may be formed to couple the MuGFET device to the semiconductor device.Type: GrantFiled: December 18, 2006Date of Patent: February 5, 2013Assignee: Infineon Technologies AGInventors: Franz Kuttner, Gerhard Knoblinger
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Publication number: 20120252172Abstract: In a method for producing a thyristor, first and second connection regions are formed on or above a substrate; the first connection region is doped with dopant atoms of a first conductivity type and the second connection region is doped with dopant atoms of a second conductivity type; first and second body regions are formed between the connection regions, wherein the first body region is formed between the first connection region and second body region, and the second body region is formed between the first body region and second connection region; the first body region is doped with dopant atoms of the second conductivity type and the second body region is doped with dopant atoms of the first conductivity type, wherein the dopant atoms are in each case introduced into the respective body region using a Vt implantation method; a gate region is formed on or above the body regions.Type: ApplicationFiled: May 29, 2012Publication date: October 4, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: Harald Gossner, Thomas Schulz, Christian Russ, Gerhard Knoblinger
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Patent number: 8236624Abstract: In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.Type: GrantFiled: November 18, 2009Date of Patent: August 7, 2012Assignee: Infineon Technologies AGInventors: Harald Gossner, Thomas Schulz, Christian Russ, Gerhard Knoblinger
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Publication number: 20110043293Abstract: The present disclosure relates voltage controlled oscillators (VCO) and digitally controlled oscillators (DCO). In one implementation, a VCO is implemented with drain extended MOS transistors (DeMOS). In another implementation, a DCO is implemented with DeMOS devices.Type: ApplicationFiled: August 19, 2009Publication date: February 24, 2011Inventors: Gerhard KNOBLINGER, Marc TIEBOUT, Franz KUTTNER
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Publication number: 20110043294Abstract: The present disclosure relates voltage controlled oscillators (VCO) and digitally controlled oscillators (DCO). In one implementation, a VCO is implemented with drain extended MOS transistors (DeMOS). In another implementation, a DCO is implemented with DeMOS devices.Type: ApplicationFiled: August 19, 2009Publication date: February 24, 2011Inventors: Gerhard KNOBLINGER, Marc TIEBOUT, Franz KUTTNER
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Publication number: 20100062573Abstract: In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.Type: ApplicationFiled: November 18, 2009Publication date: March 11, 2010Inventors: Harald Gossner, Thomas Schulz, Christian Russ, Gerhard Knoblinger
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Patent number: 7667499Abstract: In an embodiment, an apparatus includes a MuGFET device coupled to a reference source, the MuGFET device configured to receive an input signal at a gate thereof; and Also includes a further MuGFET device coupled between the MuGFET device and a first terminal of a load, a second terminal of the load coupled to a further reference source, the further MuGFET device configured to receive a further input signal at a gate thereof, and wherein the MuGFET device and the further MuGFET device are disposed above a substrate and configured to provide an output signal at the first terminal of the load.Type: GrantFiled: June 11, 2007Date of Patent: February 23, 2010Assignee: Infineon Technologies AGInventor: Gerhard Knoblinger
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Patent number: 7638370Abstract: In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.Type: GrantFiled: May 8, 2007Date of Patent: December 29, 2009Assignee: Infineon Technologies AGInventors: Harald Gossner, Thomas Schulz, Christian Russ, Gerhard Knoblinger