Abstract: A power semiconductor device comprises a wafer (2) having an active region (AR) and a termination region (TR) laterally surrounding the active region; floating field rings in the termination region; a lifetime control region comprising defects reducing a carrier lifetime; and a protecting layer (6) on the wafer. The protecting layer covers the termination region and comprises a thin portion (61) and a thick portion (62) laterally surrounding the thin portion. The thick portion covers the floating field rings. The lifetime control region (5) extends in a lateral direction throughout the active region and in the termination region throughout a portion which is covered by the thin portion and not in a portion which is covered by the thick portion. According to a fabrication method the lifetime control region is formed by irradiating the wafer (2) with ions using the protecting layer (6) as an irradiation mask.

Abstract: One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed.

Abstract: One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed.

Abstract: One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed.

Abstract: An integrated circuit is described including a first and a second plurality of conductor lines, each of the lines being separated from an adjacent line by a spacer dielectric and capped with a first and second dielectric cap material, respectively. A contact element is embedded in a covering dielectric layer with electrical contact to one of the first plurality of conductor lines in a contact portion, while being separated from a line adjacent to the contacted line only by the second cap material.

Abstract: The invention relates to a method for adapting structure dimensions during the photolithographic projection of a pattern of structure elements onto a semiconductor wafer. An exposure device (5) is provided, which can emit light in two polarization planes (32; 34). Through the choice of the degree of polarization, i.e., the ratio of the intensity in the first polarization plane (32) to the intensity in the second polarization plane (34), it is possible to alter the ratio of width (40) to length (42) of the resist structure (36) formed on the resist layer (14). A variation of approximately 30% with respect to dimensionally accurate imaging can thus be achieved in a simple manner.

Abstract: A photolithographic mask having half tone main features and perpendicular half tone assist features. One embodiment provides for the exposure of radiation-sensitive resist layers on semiconductor substrates. The mask has at least one radiation-transmissive substrate and at least one half-tone layer. The half-tone layer is used to provide main features, the main features being formed in such a way that the pattern formed by the main features is transferred into the resist layer when irradiated, and the half-tone layer is also used to provide assist features, the assist features being formed substantially perpendicular to the main features in such a way that the pattern formed by the assist features is not transferred into the resist layer when irradiated.

Abstract: A first and a second phase-shifting, semitransparent layer are formed on a substrate. The layers are patterned lithographically to form first elevated structure elements on the substrate with a first degree of transmission and second structure elements with a second degree of transmission, where the second degree of transmission is different from the first degree of transmission. Memory products can be produced with high resolution and high dimensional accuracy when the structure elements are transferred to a semiconductor substrate, by virtue of dense structure arrangements being represented by the structure elements with a high degree of transmission of more than 30% and, on the same mask, isolated structure arrangements having a low density being represented by the structure elements with a lower degree of transmission.

Abstract: An inspection system includes an illumination source configured to illuminate a blazed phase grating sample, image collection pathways and an imaging system configured to capture an image of a sample point of the blazed phase grating sample, and a controller configured to adjust the illumination source in response to an analysis of the image of the sample point to determine illumination uniformity of the inspection system.

Abstract: A system for analyzing images of a blazed phase grating sample includes an interface configured to receive images of sample points of a blazed phase grating sample obtained by an inspection system, a memory for storing the images, and a processor. Each image is named according to a sequential naming protocol that associates each image to a location on the blazed phase grating sample. The processor is configured to load the images from the memory, convert image data for each sample point to intensity values by pixel, determine a best focus by azimuth for each sample point based on the intensity values, and calculate parameters from the blazed phase grating sample based on the best focus by azimuth for each sample point.

Abstract: An exposure tool includes an illumination source, a blazed phase grating reticle, a reticle stage holding the blazed phase grating reticle, a lens system including at least one adjustable lens element, a wafer stage holding a sample, and a controller. The controller is configured to control the illumination source and the position of the blazed phase grating reticle and the lens system relative to the wafer stage to expose the sample to generate a blazed phase grating sample. The controller is configured to adjust the at least one adjustable lens element to compensate for aberrations of the lens system based on feedback generated from analyzing images of the blazed phase grating sample.

Abstract: An exposure tool includes an illumination source, a blazed phase grating reticle, a lens system, a focus sensor configured for maintaining a focus of the lens system, a stage holding a sample, and a controller. The controller is configured to control the illumination source and a position of the blazed phase grating reticle and the lens system relative to the stage to expose the sample according to a product shot map to generate a blazed phase grating sample. The controller is configured to adjust a focus offset of the exposure tool by product shot to improve focal plane fitting based on feedback generated from an analysis of images of the blazed phase grating sample.

Abstract: An inspection system includes an illumination source configured to illuminate a blazed phase grating sample, image collection pathways and an imaging system configured to capture an image of a sample point of the blazed phase grating sample, and a controller configured to adjust the illumination source in response to an analysis of the image of the sample point to determine illumination uniformity of the inspection system.

Abstract: The relative surface area sizes of portions having distinct phase-shift and transmission of light of a pattern on a phase-shift mask substantially obey the condition that the product of surface area and transmission of the electrical field strength is the same for all of the portions. Then, frequency doubling occurs due to vanishing zero order diffraction orders and in the case of high-transition attenuated phase-shift masks a large first order diffraction amplitude reveals an even an improved as compared with conventional phase-shift masks. Two-dimensional matrix-like structures particularly on attenuated or halftone phase-shift masks can be arranged to image high-density patterns on a semiconductor wafer. The duty cycles of pattern matrices can be chosen being different from one in two orthogonal directions nevertheless leading to frequency doubling.

Abstract: In the case of a mask having a structure which can be imaged on a substrate lithographically at a predetermined exposure wavelength and has at least one structure element with a width in the same order of magnitude as the exposure wavelength, the structure element is subdivided into sections which are separated from one another and whose length is in the same order of magnitude as the exposure wavelength.

Abstract: The invention relates to a method for adapting structure dimensions during the photolithographic projection of a pattern of structure elements onto a semiconductor wafer. An exposure device (5) is provided, which can emit light in two polarization planes (32; 34). Through the choice of the degree of polarization, i.e., the ratio of the intensity in the first polarization plane (32) to the intensity in the second polarization plane (34), it is possible to alter the ratio of width (40) to length (42) of the resist structure (36) formed on the resist layer (14). A variation of approximately 30% with respect to dimensionally accurate imaging can thus be achieved in a simple manner.

Abstract: A first and a second phase-shifting, semitransparent layer are formed on a substrate. The layers are patterned lithographically to form first elevated structure elements on the substrate with a first degree of transmission and second structure elements with a second degree of transmission, where the second degree of transmission is different from the first degree of transmission. Memory products can be produced with high resolution and high dimensional accuracy when the structure elements are transferred to a semiconductor substrate, by virtue of dense structure arrangements being represented by the structure elements with a high degree of transmission of more than 30% and, on the same mask, isolated structure arrangements having a low density being represented by the structure elements with a lower degree of transmission.

Abstract: Active areas of a Dynamic Random Access Memory (DRAM) formed on a semiconductor substrate are defined by buried bit lines on two sides and by conductors separated from the semiconductor substrate by electrically insulating layers on two other sides. The conductors are electrically biased during operation of the DRAM to cause portions of the semiconductor substrate therebelow to increase in majority carrier concentration and thus to inhibit inversion thereof. Each buried bit line is formed in a trench in the semiconductor substrate. Each trench houses a separate bit line and is lined with an electrical insulator and has a conductor in a bottom portion thereof.

Abstract: An item of information about the respective positions (501, 502, 601, 602) of at least two structure elements (50, 60) on a mask is provided. The displacement of the positional positions during the imaging by the lens system of the exposure apparatus, the displacement being governed by lens aberration, is measured and correction values (540, 640) are determined for each of the structure elements. Using the correction values (540, 640) the positions (501, 502, 601, 602) are changed in order to form new positions (505, 506, 605, 606) of the structure elements (50, 60) in such a way that the aberration effects can be compensated for. A mask (40) adapted to the exposure apparatus is exposed with the structures at the changed positions. The variation in the positional accuracies and the structure width distributions which is governed by the aberration of lenses is advantageously reduced.

Abstract: In a method of manufacturing a phase shift mask, an opening is produced by lithography in a second layer (32) arranged on an opaque layer (10). An etching step in which a first subregion (12) on a deep-etched surface of the transparent substrate (18) is uncovered is carried out in order for the opening to be transferred into the opaque layer (10) and into the substrate (18) below. Widening of the opening in the second layer (32) and etching so as to transfer the opening into the opaque layer (10) lead to the formation of a second subregion (14), which adjoins the recessed first subregion (12) and surrounds it in rim form, on the surface of the transparent substrate (18).