Abstract: A digital to analog (DAC) circuit that performs least significant bit (LSB) dithering comprises: a first DAC; an auxiliary code generator configured to produce an auxiliary code; an auxiliary DAC configured to receive the auxiliary code and convert the auxiliary code into an analog version of the auxiliary code; and summing circuitry to dither LSBs of the first DAC with the auxiliary code. The auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit, the auxiliary code has a smaller range than that of a range of binary-weighted LSBs of the main DAC and/or the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence.

Abstract: A digital to analog (DAC) circuit that performs least significant bit (LSB) dithering comprises: a first DAC; an auxiliary code generator configured to produce an auxiliary code; an auxiliary DAC configured to receive the auxiliary code and convert the auxiliary code into an analog version of the auxiliary code; and summing circuitry to dither LSBs of the first DAC with the auxiliary code. The auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit, the auxiliary code has a smaller range than that of a range of binary-weighted LSBs of the main DAC and/or the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence.

Abstract: Radio-frequency (RF) receivers having bandpass sigma-delta analog sigma analog-to-digital converters (ADC) designed to digitize signals in the RF domain are described. Such bandpass ADCs utilize one or more of the following techniques to enhance noise immunity and reduce power consumption: generation of in-phase (I) and quadrature (Q) paths in the digital domain, nth order resonant bandpass filtering with n>1, and signal sub-sampling in an ith Nyquist zone with i>1. Compared to RF receivers in which the I and Q paths are generated in the analog domain, these RF receivers exhibit higher IRRs because they are not susceptible to in-phase/quadrature (IQ) mismatch. Using nth order resonant bandpass filtering with n>1 attenuates unwanted image tones. The bandpass ADC-based RF receivers described herein exhibit enhanced immunity to noise, achieving for example image rejection ratios (IRR) in excess of 95 dB.

Abstract: Radio-frequency (RF) receivers having bandpass sigma-delta analog sigma analog-to-digital converters (ADC) designed to digitize signals in the RF domain are described. Such bandpass ADCs utilize one or more of the following techniques to enhance noise immunity and reduce power consumption: generation of in-phase (I) and quadrature (Q) paths in the digital domain, nth order resonant bandpass filtering with n>1, and signal sub-sampling in an ith Nyquist zone with i>1. Compared to RF receivers in which the I and Q paths are generated in the analog domain, these RF receivers exhibit higher IRRs because they are not susceptible to in-phase/quadrature (IQ) mismatch. Using nth order resonant bandpass filtering with n>1 attenuates unwanted image tones. The bandpass ADC-based RF receivers described herein exhibit enhanced immunity to noise, achieving for example image rejection ratios (IRR) in excess of 95dB.

Abstract: Radio-frequency (RF) receivers having bandpass sigma-delta analog sigma analog-to-digital converters (ADC) designed to digitize signals in the RF domain are described. Such bandpass ADCs utilize one or more of the following techniques to enhance noise immunity and reduce power consumption: generation of in-phase (I) and quadrature (Q) paths in the digital domain, nth order resonant bandpass filtering with n>1, and signal sub-sampling in an ith Nyquist zone with i>1. Compared to RF receivers in which the I and Q paths are generated in the analog domain, these RF receivers exhibit higher IRRs because they are not susceptible to in-phase/quadrature (IQ) mismatch. Using nth order resonant bandpass filtering with n>1 attenuates unwanted image tones. The bandpass ADC-based RF receivers described herein exhibit enhanced immunity to noise, achieving for example image rejection ratios (IRR) in excess of 95 dB.

Abstract: Radio-frequency (RF) receivers having bandpass sigma-delta analog sigma analog-to-digital converters (ADC) designed to digitize signals in the RF domain are described. Such bandpass ADCs utilize one or more of the following techniques to enhance noise immunity and reduce power consumption: generation of in-phase (I) and quadrature (Q) paths in the digital domain, nth order resonant bandpass filtering with n>1, and signal sub-sampling in an ith Nyquist zone with i>1. Compared to RF receivers in which the I and Q paths are generated in the analog domain, these RF receivers exhibit higher IRRs because they are not susceptible to in-phase/quadrature (IQ) mismatch. Using nth order resonant bandpass filtering with n>1 attenuates unwanted image tones. The bandpass ADC-based RF receivers described herein exhibit enhanced immunity to noise, achieving for example image rejection ratios (IRR) in excess of 95 dB.

Abstract: An apparatus for generating base band receive signals includes a first analog-to-digital converter module generating a first digital high frequency receive signal at least by sampling a first analog high frequency receive signal, a first digital signal processing module generating a first base band receive signal based on the first digital high frequency receive signal, a second analog-to-digital converter module generating a second digital high frequency receive signal at least by sampling a second analog high frequency receive signal and a second digital signal processing module generating a second base band receive signal based on the second digital high frequency receive signal. The first analog high frequency receive signal comprises first payload data at a first receive channel associated with a first carrier frequency and the second analog high frequency receive signal comprises second payload data at a second receive channel associated with a second carrier frequency.

Abstract: An apparatus for generating base band receive signals includes a first analog-to-digital converter module generating a first digital high frequency receive signal at least by sampling a first analog high frequency receive signal, a first digital signal processing module generating a first base band receive signal based on the first digital high frequency receive signal, a second analog-to-digital converter module generating a second digital high frequency receive signal at least by sampling a second analog high frequency receive signal and a second digital signal processing module generating a second base band receive signal based on the second digital high frequency receive signal. The first analog high frequency receive signal comprises first payload data at a first receive channel associated with a first carrier frequency and the second analog high frequency receive signal comprises second payload data at a second receive channel associated with a second carrier frequency.

Abstract: A continuous-time delta-sigma analog digital converter for converting an analog input signal to a digital output signal, comprising an analog filter with at least one integration capacitor, a cycled quantifier which quantifies the filtered analog signal for generating the digital output signal, and a feedback device with at least one digital analog converter, which supplies at least a first analog feedback signal to the analog filter corresponding to the value of the digital output signal. The feedback device for generating a second feedback signal corresponding to the differentiated output signal of the quantifier, comprises a switching device coupled capacitively to the integration capacitor, by means of which device corresponding charge portions are transmitted to the integration capacitor when there is a variation in the digital output signal.

Abstract: The invention relates to a continuous-time delta-sigma analog digital converter (10) for converting an analog input signal (IN) to a digital output signal (OUT), comprising an analog filter (20), which filters the analog input signal, a quantifier (30) cycled by a clock signal (CLK), which quantifier quantifies the filtered analog signal transmitted by the analog filter (20) to generate the digital output signal, and a feedback device (40) with at last one digital analog converter, which transmits at least one analog feedback signal based on the digital output signal (OUT) to the analog filter (20).

Abstract: The invention concerns a time-continuous delta-sigma analog-digital converter for the conversion of an analog input signal into a digital output signal, comprising an analog filter for the filtering of the analog input signal, a clocked operated quantiser, which contains at least one comparator (34) and which quantises the filtered analog signal outputted through the analog filter for the generation of the digital output signal, and a feedback arrangement with at least one digital-analog converter, which supplies to the analog filter at least one feedback signal on the basis of the digital output signal. According to the invention a calibration device (32) linked with the quantiser is stipulated, which is designed to determine at a predetermined point in time an offset error of the comparator (34) and subsequently to compensate for this (Itrim).

Abstract: The invention concerns a continuous-time delta-sigma analog-digital converter for the conversion of an analog input signal into a digital output signal, comprising an analog filter which filters the analog input signal and at least one externally circuited operational amplifier (OPAMP) for the formation of an integrator stage, a clock-driven quantizer, which quantizes the filtered analog signal outputted through the analog filter to generate the digital output signal, and a feedback arrangement with at least one digital-analog converter, which supplies to the analog filter at least one feedback signal on the basis of the digital output signal.

Abstract: The invention concerns a time-continuous delta-sigma analog-digital converter for the conversion of an analog input signal into a digital output signal, comprising an analog filter for the filtering of the analog input signal, a clocked operated quantiser, which contains at least one comparator (34) and which quantises the filtered analog signal outputted through the analog filter for the generation of the digital output signal, and a feedback arrangement with at least one digital-analog converter, which supplies to the analog filter at least one feedback signal on the basis of the digital output signal. According to the invention a calibration device (32) linked with the quantiser is stipulated, which is designed to determine at a predetermined point in time an offset error of the comparator (34) and subsequently to compensate for this (Itrim).

Abstract: The invention concerns a continuous-time delta-sigma analog-digital converter for the conversion of an analog input signal into a digital output signal, comprising an analog filter which filters the analog input signal and at least one externally circuited operational amplifier (OPAMP) for the formation of an integrator stage, a clock-driven quantiser, which quantises the filtered analog signal outputted through the analog filter to generate the digital output signal, and a feedback arrangement with at least one digital-analog converter, which supplies to the analog filter at least one feedback signal on the basis of the digital output signal.

Abstract: The invention relates to a continuous-time delta-sigma analog digital converter for converting an analog input signal (Vin) to a digital output signal (Vout), comprising an analog filter (20), which filters the analog input signal and has at least one integration capacitor (C1, C2, C3), a cycled quantifier (30) which quantifies the filtered analog signal output by the analog filter (20) for generating the digital output signal (Vout), and a feedback device (40) with at least one digital analog converter (42, 44), which supplies at least one analog feedback signal to the analog filter (20) on the basis of the digital output signal (Vout).

Abstract: The invention relates to a continuous-time delta-sigma analog digital converter (10) for converting an analog input signal (IN) to a digital output signal (OUT), comprising an analog filter (20), which filters the analog input signal, a quantifier (30) cycled by a clock signal (CLK), which quantifier quantifies the filtered analog signal transmitted by the analog filter (20) to generate the digital output signal, and a feedback device (40) with at last one digital analog converter, which transmits at least one analog feedback signal based on the digital output signal (OUT) to the analog filter (20).

Abstract: The invention relates to an integrated circuit arrangement with an active filter comprising transconductance stages, each being adjustable by means of a bias current to be supplied, and comprising a tuning device for tuning the filter, which tuning device adjusts the bias currents of the transconductance stages, wherein the tuning device adjusts the bias current of a first transconductance stage, for the purpose of achieving a desired characteristic of this transconductance stage, and adjusts the bias current of at least one further transconductance stage such that the transconductance of this further transconductance stage deviates from the transconductance of the first transconductance stage by a certain value.

Abstract: The invention pertains to an integrated circuit arrangement, in particular, in accordance with the CMOS technology, with at least one transconductance amplifier (1) in order to generate a current signal (outp, outm) from an input voltage signal (inp-inm), wherein the transconductance amplifier consists of a first transconductance stage (gm1) and a second transconductance stage (gm2) that are connected in parallel, wherein the first transconductance stage (gm1) has a transconductance that is essentially defined by an ohmic resistance and the second transconductance stage (gm2) has an adjustable transconductance that is essentially defined by a transistor arrangement, and wherein the transconductance of the first transconductance stage (gm1) is higher than the transconductance of the second transconductance stage (gm2).

Abstract: The invention relates to an integrated circuit arrangement with an active filter comprising transconductance stages, each being adjustable by means of a bias current to be supplied, and comprising a tuning device for tuning the filter, which tuning device adjusts the bias currents of the transconductance stages, wherein the tuning device adjusts the bias current of a first transconductance stage, for the purpose of achieving a desired characteristic of this transconductance stage, and adjusts the bias current of at least one further transconductance stage such that the transconductance of this further transconductance stage deviates from the transconductance of the first transconductance stage by a certain value, wherein the bias current (0.

Abstract: The invention pertains to an integrated circuit arrangement, in particular, in accordance with the CMOS technology, with at least one transconductance amplifier (1) in order to generate a current signal (outp, outm) from an input voltage signal (inp−inm), wherein the transconductance amplifier consists of a first transconductance stage (gm1) and a second transconductance stage (gm2) that are connected in parallel, wherein the first transconductance stage (gm1) has a transconductance that is essentially defined by an ohmic resistance and the second transconductance stage (gm2) has an adjustable transconductance that is essentially defined by a transistor arrangement, and wherein the transconductance of the first transconductance stage (gm1) is higher than the transconductance of the second transconductance stage (gm2).