Abstract: A method and a device for interpolating or decimating a signal is provided, the signal being processed by a plurality of signal processing means connected in series, which at least comprise means for increasing or reducing a clock rate of the signal and filtering means. To achieve adaptation to different operating modes or transmission standards, individual portions of the signal processing means connected in series can be bridged by bypasses. In addition, filtering parameters of the filtering means can be varied and factors, by which a clock rate of the signal is increased or reduced, can be changed.

Abstract: The invention relates to a method for ascertaining a resistance value (Z) between a first contact (2) and a second contact (3) in a subscriber line interface circuit (4), where a protective circuit (9) for protecting the subscriber line interface circuit (4) against overvoltages is provided between the two contacts (2, 3) and comprises a parallel circuit containing a protective capacitor (5) with two resistors (7, 8) connected in series via a node (K), the node (K) being connected to a third contact (10) in the subscriber line interface circuit (4), where the method has the following steps: a predetermined charging voltage (UCharge) is applied to the protective capacitor (5); a threshold voltage (UTH) is calculated on the basis of the resistance values (R1, R2) of the two resistors (7, 8) and the applied charging voltage (UCharge); a measured voltage (UM) tapped off across one of the two resistors (7, 8) is measured while the protective capacitor (5) is discharging; the measured voltage (UM) is compared with

Abstract: The invention relates to a method and an apparatus for controlling a digital signal processor having a number of arithmetic units (1a, 1b) which process a program (8). A control unit (5) is provided for independent control of the individual arithmetic units (1a, 1b), which control unit (5) reads and evaluates the flags (9a, 9b) which are specific to the arithmetic units, and deactivates those arithmetic units (1a, 1b) whose associated flag is not set, so that a subroutine is carried out only by those arithmetic units (1a, 1b) whose flags are set.

Abstract: The invention relates to a method for ascertaining a resistance value (Z) between a first contact (2) and a second contact (3) in a subscriber line interface circuit (4), where a protective circuit (9) for protecting the subscriber line interface circuit (4) against overvoltages is provided between the two contacts (2, 3) and comprises a parallel circuit containing a protective capacitor (5) with two resistors (7, 8) connected in series via a node (K), the node (K) being connected to a third contact (10) in the subscriber line interface circuit (4), where the method has the following steps: a predetermined charging voltage (UCharge) is applied to the protective capacitor (5); a threshold voltage (UTH) is calculated on the basis of the resistance values (R1, R2) of the two resistors (7, 8) and the applied charging voltage (UCharge); a measured voltage (UM) tapped off across one of the two resistors (7, 8) is measured while the protective capacitor (5) is discharging; the measured voltage (UM) is compared with

Abstract: A grounding key detecting device and method for interference-proof detection of the operation of grounding keys in telephones. A circuit that detects the operation of a grounding key includes a current detection device configured to detect a current flowing when the grounding key is in operation, a comparator configured to compare the detected current with at least one threshold value, and a monitoring circuit configured to detect a first period when the current exceeds the threshold value, detect a second period when the current drops below the threshold value, and output a grounding key detection signal when the first period is greater than the second period.

Abstract: A method and a device for interpolating or decimating a signal is provided, the signal being processed by a plurality of signal processing means connected in series, which at least comprise means for increasing or reducing a clock rate of the signal and filtering means. To achieve adaptation to different operating modes or transmission standards, individual portions of the signal processing means connected in series can be bridged by bypasses. In addition, filtering parameters of the filtering means can be varied and factors, by which a clock rate of the signal is increased or reduced, can be changed.

Abstract: A method for resynchronizing a clock signal, includes the steps of defining a presettable clock signal, dividing a first clock signal having a first frequency with a programmable digital frequency divider to produce a second clock signal having a second frequency, measuring the second clock signal with a digital control circuit, and programming a programmable digital frequency divider with the digital control circuit, such that the second clock signal corresponds to the presettable clock signal.

Abstract: Method for measuring a load impedance (ZL) of a load circuit which is connected to an SLIC circuit (6) of an analog terminal connection of a terminal device, having the following steps: specifically a digital toll signal (x1) is generated by means of a Codec circuit (13) connected to the SLIC circuit (6), said toll signal (x1) being converted into an analog toll signal; the analog toll signal is output by the SLIC circuit (6) to the load circuit; an analog voltage which is brought about at the terminal connection (4,5) of the terminal device of the SLIC circuit (6) via the analog toll signal is sensed; the digital toll signal (x1) is filtered by means of an adaptive filter (39) which is provided in the Codec circuit (13) and has adjustable filter coefficients (g1, g2) for generating a filtered digital comparison signal (yv) which is converted into an analog comparison voltage (Uv); the filter coefficients (g1, g2) of the adaptive filter (39) are adjusted until the analog comparison voltage (Uv) and the analog

Abstract: The invention relates to a method and an apparatus for controlling a digital signal processor having a number of arithmetic units (1a, 1b) which process a program (8). A control unit (5) is provided for independent control of the individual arithmetic units (1a, 1b), which control unit (5) reads and evaluates the flags (9a, 9b) which are specific to the arithmetic units, and deactivates those arithmetic units (1a, 1b) whose associated flag is not set, so that a subroutine is carried out only by those arithmetic units (1a, 1b) whose flags are set.

Abstract: Method for measuring a load impedance (ZL) of a load circuit which is connected to an SLIC circuit (6) of an analog terminal connection of a terminal device, having the following steps: specifically a digital toll signal (x1) is generated by means of a Codec circuit (13) connected to the SLIC circuit (6), said toll signal (x1) being converted into an analog toll signal; the analog toll signal is output by the SLIC circuit (6) to the load circuit; an analog voltage which is brought about at the terminal connection (4,5) of the terminal device of the SLIC circuit (6) via the analog toll signal is sensed; the digital toll signal (x1) is filtered by means of an adaptive filter (39) which is provided in the Codec circuit (13) and has adjustable filter coefficients (g1, g2) for generating a filtered digital comparison signal (yv) which is converted into an analog comparison voltage (Uv); the filter coefficients (g1, g2) of the adaptive filter (39) are adjusted until the analog comparison voltage (Uv) and the analog