Abstract: An improved DSP has two internal data buses with two MAC units each receiving data from its respective data bus. A shifter is interposed between the multiply unit and the ALU and accumulate unit. The improved DSP also has a multiplexer interposed between one of the MAC units and the two data buses. The improved DSP is optimized to decode a received digital signal encoded in accordance with the Viterbi algorithm, wherein the DSP calculates a first pair of binary signals C.sub.2n and C.sub.2n+1 a Viterbi butterfly based upon a second pair of binary C.sub.n and C.sub.n+m/2, and a transitional signal a, in accordance with: C.sub.2n =minimum (C.sub.n +a, C.sub.n+m/2 -a); C.sub.2n+1 =minimum (C.sub.n -a, C.sub.n+m/2 +a).

Abstract: The multiply/divide circuit uses an exclusive OR function of an ALU in a DSP. The result of the exclusive OR function through accumulators and shift registers which recycle the shifted signals back to the ALU, can be made to perform the multiply or divide function. When used in a DSP for telecommunication purposes, the multiply/divide circuit can perform convolution encoding and cyclic redundancy check, among other functions, specifically for the telecommunication application.

Abstract: A composite encoder/syndrome generating circuit computes both check symbols and error syndromes using a single set of multiplier devices with varying tap weights having values that provide a maximum preselected error correction capability but is readily adjustable, such as by programmable latches, to eliminate from the circuit selectable multiplier devices to reduce the error correction capability without requiring a change in the tap weight values. The circuit may be used to increase or decrease error correction capability (a) according to which of a plurality of concentric bands of recording tracks is being accessed in a banded direct access data storage device, (b) according to noise level as sensed in a data communications channel having an output subject to noise, or (c) according to changes in sending rates in a sending device that sends data at variable rates.

Abstract: A parallel processing circuit and a digital signal processor employing such a parallel circuit employs a plurality of identical multiply and accumulate (MAC) processing units. Two input signals are supplied to each of the MAC processing units. In one embodiment, a delay or a shift register delays one of the input digital signal from one MAC to another MAC. A plurality of different processed signals can be generated simultaneously based upon the supplied input digital signals, greatly increasing processing capability without increasing clock speed or increasing bandwidth access to a memory.

Abstract: A Viterbi decoder having a recursive processor modified to process each node in a trellis of a partial response coded signal to shift the branch metric additions over the node to effectuate compare, select, add operation order on the predecessor survivor metrics terminating in that node, to compare the metrics of the predecessor sequences terminating in the node, to select a survivor sequence, and to add the shifted branch metrics to the metric of the selected survivor sequence.

Abstract: A divide circuit having bit level pipeline capability uses an array of bit level carry save adders with each carry save adder having a corresponding absolute value bit level circuit. In one or two's complement notation, the carry save adders subtract the binary values supplied thereto and generates an intermediate binary signal which is supplied to the absolute value circuit. The absolute value circuit determines the absolute value of the binary number supplied thereto. The circuit performs division in accordance with the following algorithm:Q.sub.w 1I=W-1 to 0N=N-DS=Signbit (N)Q.sub.I =S (EXOR) Q.sub.I+1N=.vertline.N.vertline.D=D/2ENDA recursive divide circuit employing an array of carry save adders and absolute value bit level circuits achieves full pipeline bit level capability.

Abstract: A multiply and divide circuit having full bit level pipeline capability uses an array of bit level carry-save adders with each carry-save bit adder having a corresponding absolute value bit circuit. In one or two's complement notation, the carry-save adders subtract the binary values supplied thereto and generate an intermediate binary signal which is supplied to the absolute value circuit. The absolute value circuit determines the absolute value of the binary numbers supplied thereto. In one mode of operation, the circuit can be used to perform division. In another mode of operation, the circuit can be used to perform multiply and accumulate operation, again with bit level pipeline capability.

Abstract: A method for implementing the Viterbi algorithm (Viterbi decoder) for very high data rates/decoding rates. The trellis diagram (original trellis diagram) of the Markov process, the original trellis diagram being the basis of such implementation, is considered over a greater period. Transitions of the original trellis diagram are combined in one multi-step transition (multi-step trellis diagram) per each M. The number of transition branches, which rise exponentially, in such a process with M, is reduced to a smaller number by exploiting fundamental properties of the original trellis diagram forming the basis of the multi-step transitions. This eliminates non-optimal transition branches irrespective of the change from one multi-step transition to another.