Abstract: An integrated circuit structure to be built on a semiconductor substrate wafer for the purpose of undertaking a quality check of the wafer has a plurality of field effect transistors laterally disposed in the same close adjacency as transistors which are to be manufactured on a chip using the wafer material. Each field effect transistor has its own well structure, its own source structure, and its own drain structure. The individual field effect transistors have pads allocated thereto at an edge of the structure. Each transistor source/drain structure is connected to the pads by a conductor, the totality of these conductors having width and/or length dimensions so that each run has approximately the same resistance. Only one common gate conductor for all of the transistors is provided.