Abstract: In order to create a noise elimination device for the detection of the vertical sync pulse in video signals, which has a very fast locking behavior and in which additional components can be integrated easily, which components can measure fundamental parameters of the underlying composite video signal, it is proposed that the device comprises a vertical pulse detector (12), which detects successive vertical sync pulses in the composite video signal and a VPLL (vertical phase locked loop), which comprises at least a phase detector (18) that produces a phase error, at least a loop filter (20), at least an oscillator (16) on which the output signal of the vertical pulse detector is present as an input signal and which oscillator produces a clock signal phase-synchronized with the input signal, whereas the oscillator (16) is a counter which counts with an approximately constant clock frequency, while the length of an oscillation period of the oscillator (16) is determined by the change in its count due to a correc

Abstract: In order to create a noise elimination device for the detection of the vertical sync pulse in video signals, which has a very fast locking behavior and in which additional components can be integrated easily, which components can measure fundamental parameters of the underlying composite video signal, it is proposed that the device comprises a vertical pulse detector (12), which detects successive vertical sync pulses in the composite video signal and a VPLL (vertical phase locked loop), which comprises at least a phase detector (18) that produces a phase error, at least a loop filter (20), at least an oscillator (16) on which the output signal of the vertical pulse detector is present as an input signal and which oscillator produces a clock signal phase-synchronized with the input signal, whereas the oscillator (16) is a counter which counts with an approximately constant clock frequency, while the length of an oscillation period of the oscillator (16) is determined by the change in its count due to a correc

Abstract: A synchronizing arrangement for a picture display device includes a synchronizing signal separating stage in which horizontal synchronizing pulses are recovered from a television signal applied to the synchronizing arrangement. In addition, the synchronizing arrangement includes a horizontal synchronizing circuit, more specifically a phase-locked loop, to which the horizontal synchronizing pulses are applied for the purpose of synchronization. When, switching criterion is present for a first presettable number of picture lines, the horizontal synchronizing circuit is switched to a fixed rated frequency. When the switching criterion is not satisfied anymore, the horizontal synchronizing circuit is switched back to synchronization by the horizontal synchronizing pulses after a second presettable number of picture lines.

Abstract: A signal detector circuit arrangement for detecting synchronizing pulses contained in a digital television signal by the use of a separating stage wherein, during the time intervals in which television signal portions are separated in the separating stage and at the same time an instantaneous sampling value exceeds a stored sampling value in the direction of the level of the synchronizing pulses, the stored sampling value is replaced by the instantaneous sampling value and simultaneously a marker pulse is generated. In each time interval between consecutive synchronizing pulses, the stored sampling value is erased at a presettable instant which is identical for all the time intervals. The final marker pulse of such an erasing procedure marks a detected synchronizing pulse.

Abstract: A digital synchronizing arrangement for a picture display device includes a synchronizing signal separator stage in which horizontal sync pulses are derived from a digital television signal applied to the synchronizing arrangement and which includes a horizontal synchronizing signal. A phase-locked loop receives the horizontal sync pulses for its synchronization. For the purpose of suppressing signal disturbances, a pulse of a first switching signal derived from the phase-locked loop is generated each time at the expected instants of the horizontal sync pulses. Furthermore, a pulse of a second switching signal is generated each time in a predetermined time interval after each pulse of the first switching signal. The first horizontal sync pulse which occurs during a pulse of the first switching signal is applied to the phase-locked loop, whereas horizontal sync pulses subsequently occurring in the interval until the next pulse of the second switching signal are not applied to the phase-locked loop.

Abstract: A digital phase-locked loop comprises a phase comparator, a controllable oscillator whose output signal is compared with an input signal in the phase comparator, and a loop filter preceding the oscillator. The filter comprises a clocked input register for storing the last phase-measuring value of the phase comparator, and an integrator which comprises a clocked register whose output signal is fed back to the register input. When the input signal of the phase comparator is absent or disturbed, a switching signal is generated which immediately erases the input register in the loop filter and after whose appearance the register in the integrator of the loop filter is reset to zero within a limited number of clock cycles.

Abstract: In a digital circuit for detecting horizontal or vertical synchronizing pulses in a digital video signal, the video signal is applied to a level detector which supplies an extreme value signal which indicates the level of the synchronizing pulse at the end of a time interval. The extreme value signal represents the extreme value of the signal which has hitherto occurred in a time interval equal the time between two consecutive synchronizing pulses. In each period between two consecutive synchronizing pulses a new time interval is started at a predetermined instant outside the blanking interval. In order to generate a comparison signal, the extreme value signal is continuously reduced by a predetermined amount. The comparison signal and the digital video signal delayed by several sample clock periods are applied to a comparator which supplies a synchronizing signal during those periods when amplitude level of the delayed digital video signal is higher than the level of the comparison signal.