Abstract: A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.

Abstract: A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.

Abstract: A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.

Abstract: A memory module system, a memory module, a buffer device, a memory module printed circuit board, and to a method for operating a memory module is disclosed. In one embodiment, the memory module system includes at least a first, a second, and a third memory module. The first memory module is connected with the second memory module via a first connection and with the third memory module via a second connection, and is designed and equipped such that data, address, and/or control signals received by the first memory module are transmitted to the second memory module via the first connection and to the third memory module via the second connection.

Abstract: One embodiment provides a system including a communications channel, a first channel master, and a second channel master. The first channel master is configured to obtain latency values and maintain a first schedule of data traffic on the communications channel based on the latency values. The second channel master is configured to obtain the latency values and maintain a second schedule of data traffic on the communications channel based on the latency values. The first channel master manages data on the communications channel via the first schedule and the second channel master manages data on the communications channel via the second schedule.

Abstract: A memory buffer for an FB-DIMM having a first input/output interface for communicating with a memory controller at a first payload data rate and a second input/output interface for communicating with memory packages at a second payload data rate, wherein a relation of the first payload data rate to the second payload data is greater than 10.

Abstract: A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.

Abstract: A memory buffer for an FB-DIMM having a first input/output interface for communicating with a memory controller at a first payload data rate and a second input/output interface for communicating with memory packages at a second payload data rate, wherein a relation of the first payload data rate to the second payload data is greater than 10.

Abstract: A communication unit is configured to operate with a memory module. The communication unit includes a first connection configured to couple to a memory controller, a second connection configured to couple to memory of the memory module, and a search engine. The search engine includes a search routine activatable by a search request received via the first connection, the search routine when activated searching a memory connected to the second connection for a search pattern received via the first connection.

Abstract: One embodiment provides a system including a communications channel, a first channel master, and a second channel master. The first channel master is configured to obtain latency values and maintain a first schedule of data traffic on the communications channel based on the latency values. The second channel master is configured to obtain the latency values and maintain a second schedule of data traffic on the communications channel based on the latency values. The first channel master manages data on the communications channel via the first schedule and the second channel master manages data on the communications channel via the second schedule.

Abstract: A memory module system, a memory module, a buffer device, a memory module printed circuit board, and to a method for operating a memory module is disclosed. In one embodiment, the memory module system includes at least a first, a second, and a third memory module. The first memory module is connected with the second memory module via a first connection and with the third memory module via a second connection, and is designed and equipped such that data, address, and/or control signals received by the first memory module are transmitted to the second memory module via the first connection and to the third memory module via the second connection.

Abstract: A control unit for a memory module includes a usage determination unit configured to determine accumulated usage information and a control circuit coupled to the usage determination unit. The control circuit is configured to compare the accumulated usage information and usage limit information defining a limit for a usage of the memory module, and to control the operation of the control unit based on a result of the comparison.

Abstract: A method of error correction for a memory arrangement includes dividing information to be written to the memory arrangement into n data blocks of m bits each, writing the n data blocks to at least one memory module of the memory arrangement, determining a redundant data block based on the n data blocks, writing the redundant data block to a further memory module of the memory arrangement, reading the n data blocks, and checking for errors in the read n data blocks including detecting a faulty data block in the read n data blocks. If an error is detected, the method includes reading the redundant information in advance from the at least one further memory module and determining all bits of the faulty data block from the n data blocks and the redundant data block.

Abstract: A semiconductor arrangement includes a first control unit, a second control unit and at least one memory module. Between the first control unit and the at least one memory module and between the second control unit and the at least one memory module, data can be transferred both in a first direction and in a second direction. The at least one memory module includes a first input interface for receiving data from a first direction, a first output interface for transmitting data in a second direction, a second input interface for receiving data from the second direction, and a second output interface for transmitting data in the first direction. In order to transmit and receive data in the first and second direction, respectively, in each case first and second input interfaces and in each case first and second output interfaces are provided in the case of the first and in the case of the second control unit.

Abstract: A memory module includes a memory core configured to read and write data. A first input interface is configured to receive write or command data from a forward direction and to receive read data from the forward direction. A first output interface is configured to send read data in a reverse direction and to send write or command data in the reverse direction. A second input interface is configured to receive read data from the reverse direction and to receive write or command data from the reverse direction. A second output interface is configured to send write or command data in the forward direction and to send read data in the forward direction.

Abstract: The invention relates to an apparatus for supplying divers with artificial respiratory gas mixtures with a counterlung, which can be fixed to a diver, which is hung on gimbals, which is adjusted independently of the particular floating position of the diver and which collects his exhaled gas. For the construction of a completely closed respiratory gas circuit system, it is constructed as a single-chamber container with a bottom opening and which uses the ambient water as the sealing fluid. The container is provided with a gas outlet connection arranged above the liquid level in the inner area of the container, which can be closed by means of a shutoff device controlled by the rising liquid level and which is connected by means of a waste gas hose line with the surface of the water or the inner area of a diving chamber or bell.