Abstract: A monolithically integrated signal processing circuit comprising a signal series branch connected between a signal input terminal and a signal output terminal; a reference potential terminal; a series capacitor inserted in serial manner in the signal series branch and having a parasitic capacitance acting like a capacitor that is connected between a first electrode of the series capacitor directed towards the signal input terminal and the reference voltage terminal; and a first parallel capacitor connected between the first electrode of the series capacitor and the reference potential terminal; with the first parallel capacitor being constituted at least in part by the parasitic capacitance.

Abstract: An analog-signal to square-wave-signal reshaping system for threshold-dependent reshaping of an analog input signal to a square wave signal; comprising an offset-inflicted reshaping circuit having a signal input adapted to be fed with the analog input signal, a reference input adapted to be fed with a reference voltage determining the reshaping threshold, and a signal output from which the square wave signal is available; an offset storage circuit connected to the signal input of the reshaping circuit and adapted to store a charging voltage corresponding to the offset voltage of the reshaping circuit, with this charging voltage being adapted to be superimposed on the analog input signal for offset compensation; a controllable switch circuit which in a first switching state takes no influence on the reshaping function of the reshaping circuit and, for the purpose of offset compensation, in a second switching state interrupts the reshaping operation of reshaping circuit and effects charging of the offset storag

Abstract: An electric circuit having a switchable feedback branch switchable between a first feedback state, in which the circuit arrangement has a frequency response that is stable with respect to an oscillation tendency, and a second feedback state, in which the circuit arrangement has a frequency response that is unstable with respect to an oscillation tendency. The circuit includes a switchable frequency response compensation circuit which during the first feedback state of the feedback branch can be controlled to an ineffective state and during the second feedback state of the feedback branch can be controlled to an effective state, and in the effective state causes such compensation of the frequency response of the circuit arrangement in the second feedback state that the circuit arrangement in the second feedback state remains stable with respect to an oscillation tendency.

Abstract: A method of phase synchronization of a bit rate clock signal generated on a receiver side with a biphase-modulated digital RDS signal that is demodulated on the receiver side with both signals having the same bit rate. The bits of both the RDS signal and the bit rate clock signal are each composed of two half bits having different digital potential values. The first or the second RDS half bit has a high digital value and the other RDS half bit has a low digital value based on which one of two logic values "1" and "0" is represented by the respective RDS bit. At a first time coinciding with the time of a rising and/or falling edge of a bit of the RDS signal, the digital value of the bit rate clock signal is measured as a first sample value, and at a second time shifted from the first time by a delay time that is shorter than a half bit duration, the digital value of the bit rate clock signal is measured as a second sample value.

Abstract: A method of assessing the quality and/or existence of a biphase-modulated digital RDS signal in a radio signal broadcast by a radio transmitter and received by a radio receiver equipped for RDS, in which a bit rate clock signal is produced on the receiver side whose bit rate is identical to that of the RDS signal, the bits both of the RDS signal and of the bit rate clock signal are each composed of two half bits, and of the two RDS half bits belonging to an RDS bit, one has a positive phase and the other one has a negative phase, and in which, for quality or existence assessment, the number of positive phase signs and the number of negative phase signs are determined which are each contained in the RDS signal during the half bit periods of a predetermined number of n adjacent half bits of the bit rate clock signal, and the RDS signal, depending on whether or not the ratio between the number of positive phase signs ascertained and the number of negative phase signs ascertained corresponds to a predetermined nu

Abstract: A method of and an apparatus for phase synchronization of a bit rate clock signal generated in an RDS receiver with a digital RDS signal demodulated on the receiver side, in which both the bit rate clock signal and the RDS signal have the same bit rate. Upon turning on of the RDS receiver and/or switching over of the same to a transmitter receiving frequency different from that received so far, a control signal is generated which, upon occurrence of the next rising edge or, alternatively, of the next falling edge of the RDS signal, effects such a phase angle shift of the bit rate clock signal that the bit rate clock signal, starting from that occurrence, is in phase synchronism with the RDS signal.

Abstract: A method of demodulating a biphase modulated signal is implemented by first establishing a reference phase angle level. The biphase modulated signal contains a series of bits, each bit having first and second half-bits. The half-bits are represented by opposite phase angle levels. First and second phase angle levels correspond to the first and second half-bits respectively. After the levels associated with first and second half-bits are measured, the two levels are compared. A binary value is assigned to each pair of first and second half-bits based on the relationship of their respective levels. For example, a high phase angle level followed by a low level, can represent the binary value "1", and vice versa.