Patents by Inventor Gerhard Sollner

Gerhard Sollner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11588218
    Abstract: Methods and apparatus for a frequency selective limiter (FSL) having a magnetic material substrate that tapers in thickness and supports a transmission line that has segments and bends. The segments, which differ in width and are substantially parallel to each other, such that each segment traverses the substrate on a constant thickness of the substrate.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: February 21, 2023
    Assignee: Raytheon Company
    Inventors: Matthew A. Morton, Gerhard Sollner, Jason D. Adams, Poornima Varadarajan, Evelina Aleksandro Polyzoeva, Thomas M. Hartnett
  • Publication number: 20230052113
    Abstract: Methods and apparatus for a frequency selective limiter (FSL) having a magnetic material substrate that tapers in thickness and supports a transmission line that has segments and bends. The segments, which differ in width and are substantially parallel to each other, such that each segment traverses the substrate on a constant thickness of the substrate.
    Type: Application
    Filed: August 11, 2021
    Publication date: February 16, 2023
    Applicant: Raytheon Company
    Inventors: Matthew A. Morton, Gerhard Sollner, Jason D. Adams, Poornima Varadarajan, Evelina Aleksandro Polyzoeva, Thomas M. Hartnett
  • Publication number: 20220404550
    Abstract: A technology is described for a Photonic Integrated Circuit (PIC) radio frequency (RF) oscillator. The PIC RF oscillator can comprise an optical gain media coupled to a first mirror and configured to be coupled to the PIC. The PIC can comprise a first optical cavity located within the PIC, a tunable mirror to form a first optical path between the first mirror in the gain media and the first tunable mirror, and a frequency tunable intra-cavity dual tone resonator positioned within the first optical cavity to constrain the first optical cavity having a common optical path to produce tow primary laser tones with a tunable frequency spacing. A photo detector is optically coupled to the PIC and configured to mix the two primary laser tones to form an RF output signal with a frequency selected by the tunable frequency spacing of the two primary tones.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 22, 2022
    Inventors: Moe D. Soltani, Ken Dinndorf, Jack W. Holloway, Gerhard Sollner
  • Patent number: 10707547
    Abstract: A frequency selective limiter (FSL) is provided having a transmission line structure with a tapered width. The FSL includes a magnetic material having first and second opposing surfaces. A first conductor is disposed on the first surface of the magnetic material, where a width of the first conductor decreases from a first end of the FSL to a second end of the FSL along a length of the FSL. Two second conductors are disposed on the second surface of the magnetic material, where a width of a gap between the two second conductors decreases from the first end of the FSL to the second end of the FSL along a length of the FSL. The first conductor and two second conductors form a biplanar waveguide transmission line.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 7, 2020
    Assignee: Raytheon Company
    Inventors: Matthew A. Morton, Gerhard Sollner, Jason C. Soric
  • Patent number: 10608310
    Abstract: A frequency selective limiter (FSL) having an input port and an output port can comprise a plurality of vertically stacked transmission line structures. Each of the transmission line structures can be electrically coupled to a transmission line structure disposed directly above it and with a first one of the plurality of vertically stacked transmission line structures having one end corresponding to the FSL input port and a second one of the plurality of vertically stacked transmission line structures having one end corresponding to the FSL output port. Each of the plurality of vertically stacked transmission line structures can comprise a magnetic material having first and second opposing surfaces and one or more conductors disposed on at least one of the surfaces of the magnetic material.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: March 31, 2020
    Assignee: Raytheon Company
    Inventors: Matthew A. Morton, Jason C. Soric, Gerhard Sollner
  • Publication number: 20190393578
    Abstract: A frequency selective limiter (FSL) is provided having a transmission line structure with a tapered width. The FSL includes a magnetic material having first and second opposing surfaces. A first conductor is disposed on the first surface of the magnetic material, where a width of the first conductor decreases from a first end of the FSL to a second end of the FSL along a length of the FSL. Two second conductors are disposed on the second surface of the magnetic material, where a width of a gap between the two second conductors decreases from the first end of the FSL to the second end of the FSL along a length of the FSL. The first conductor and two second conductors form a biplanar waveguide transmission line.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 26, 2019
    Applicant: Raytheon Company
    Inventors: Matthew A. Morton, Gerhard Sollner, Jason C. Soric
  • Patent number: 10461384
    Abstract: A frequency selective limiter (FSL) is provided having a transmission line structure with a tapered width. The FSL includes a substrate having a magnetic material, a signal (or center) conductor disposed on the substrate and first and second ground plane conductors disposed on the substrate. The signal conductor having a first end with a first width and a second end with a second different width such that the signal conductor is provided having a taper between the first and second ends of the signal conductor. First and second ground plane conductors are spaced apart from first and second edges of signal conductor, respectively, by a distance that changes from the first end of signal conductor to the second end of signal conductor such that signal conductor, and first and second ground plane conductors form a co-planar waveguide transmission line.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: October 29, 2019
    Assignee: Raytheon Company
    Inventors: Matthew A. Morton, Gerhard Sollner
  • Publication number: 20180366803
    Abstract: A frequency selective limiter (FSL) is provided having a transmission line structure with a tapered width. The FSL includes a substrate having a magnetic material, a signal (or center) conductor disposed on the substrate and first and second ground plane conductors disposed on the substrate. The signal conductor having a first end with a first width and a second end with a second different width such that the signal conductor is provided having a taper between the first and second ends of the signal conductor. First and second ground plane conductors are spaced apart from first and second edges of signal conductor, respectively, by a distance that changes from the first end of signal conductor to the second end of signal conductor such that signal conductor, and first and second ground plane conductors form a co-planar waveguide transmission line.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Applicant: Raytheon Company
    Inventors: Matthew A. Morton, Gerhard Sollner
  • Patent number: 9711839
    Abstract: The present disclosure is directed towards a frequency selective limiter having a first magnetic material disposed over a first dielectric material and a strip conductor disposed over the magnetic material. In some embodiments, the frequency selective limiter includes a second magnetic material disposed over the strip conductor and a second dielectric material disposed over the second magnetic material. The first and second dielectric material may have a lower relative permittivity than the first and second magnetic material. In an embodiment, the frequency selective limiter includes a slow wave structure disposed to magnetically couple a magnetic field, produced by electromagnetic energy propagating through the slow wave structure, into the magnetic material.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: July 18, 2017
    Assignee: Raytheon Company
    Inventors: Matthew A. Morton, Gerhard Sollner
  • Publication number: 20160181679
    Abstract: The present disclosure is directed towards a frequency selective limiter having a first magnetic material disposed over a first dielectric material and a strip conductor disposed over the magnetic material. In some embodiments, the frequency selective limiter includes a second magnetic material disposed over the strip conductor and a second dielectric material disposed over the second magnetic material. The first and second dielectric material may have a lower relative permittivity than the first and second magnetic material. In an embodiment, the frequency selective limiter includes a slow wave structure disposed to magnetically couple a magnetic field, produced by electromagnetic energy propagating through the slow wave structure, into the magnetic material.
    Type: Application
    Filed: January 15, 2016
    Publication date: June 23, 2016
    Inventors: Matthew A. Morton, Gerhard Sollner
  • Patent number: 9231064
    Abstract: A semiconductor structure having: a Group III-N channel layer, a Group III-N top-barrier polarization-generating layer forming a heterojunction with an upper surface of the channel layer; and a Group III-N back-barrier polarization-generating layer forming a heterojunction with a lower surface of the channel layer. The channel layer has disposed therein a predetermined n-type conductive dopant.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: January 5, 2016
    Assignee: Raytheon Company
    Inventors: Shahed Reza, Eduardo M. Chumbes, Thomas E. Kazior, Gerhard Sollner
  • Publication number: 20120326902
    Abstract: A multi-channel time interleaved ADC (TIADC) provides for offset estimation and correction. The correction is accomplished through analog adjustment of offset rather than by digital correction of their outputs. In certain aspects, polarity reversal circuits may be used to further improve performance.
    Type: Application
    Filed: September 5, 2012
    Publication date: December 27, 2012
    Inventors: Michael P. Anthony, Gerhard Sollner, Lawrence J. Kushner
  • Patent number: 8269657
    Abstract: A multi-channel time interleaved ADC (TIADC) provides for offset estimation and correction. The correction is accomplished through analog adjustment of offset rather than by digital correction of their outputs. In certain aspects, polarity reversal circuits may be used to further improve performance.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: September 18, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Michael P. Anthony, Gerhard Sollner, Lawrence J. Kushner
  • Patent number: 8098182
    Abstract: A cable gateway, such as compatible with version 3.0 of the Data Over Cable Service Interface Specifications and other audiovisual standards, that uses an analog front end having a charge-domain analog-to-digital converter that uses a charge-domain pipeline of at least two stages.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: January 17, 2012
    Assignee: Intersil Americas Inc.
    Inventors: T. C. L. Gerhard Sollner, Michael P. Anthony, Maher Matta
  • Publication number: 20110102228
    Abstract: A multi-channel time interleaved ADC (TIADC) provides for offset estimation and correction. The correction is accomplished through analog adjustment of offset rather than by digital correction of their outputs. In certain aspects, polarity reversal circuits may be used to further improve performance.
    Type: Application
    Filed: June 18, 2010
    Publication date: May 5, 2011
    Applicant: Intersil Americas, Inc.
    Inventors: Michael P. Anthony, Gerhard Sollner, Lawrence J. Kushner
  • Patent number: 7924208
    Abstract: A low-power communication interface, such as used with 10 Gigabit Ethernet, that uses an analog front end having a charge-domain analog-to-digital converter that uses a charge-domain pipeline.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: April 12, 2011
    Assignee: Kenet, Inc.
    Inventors: T.C.L. Gerhard Sollner, Michael P. Anthony
  • Patent number: 7846760
    Abstract: A method and structure of providing a doped plug to improve the performance of CCD gaps is discussed. A highly-doped region is implemented in a semiconductor, aligned beneath a gap. The plug provides a highly-conductive region at the semiconductor surface, therefore preventing the development of a region where potential is significantly influenced by surface charges.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: December 7, 2010
    Assignee: Kenet, Inc.
    Inventors: William D. Washkurak, Michael P. Anthony, Gerhard Sollner
  • Publication number: 20100117883
    Abstract: A cable gateway, such as compatible with version 3.0 of the Data Over Cable Service Interface Specifications and other audiovisual standards, that uses an analog front end having a charge-domain analog-to-digital converter that uses a charge-domain pipeline of at least two stages.
    Type: Application
    Filed: November 10, 2009
    Publication date: May 13, 2010
    Applicant: Intersil Americas Inc.
    Inventors: T.C.L. Gerhard Sollner, Michael P. Anthony
  • Publication number: 20080297393
    Abstract: A low-power communication interface, such as used with 10 Gigabit Ethernet, that uses an analog front end having a charge-domain analog-to-digital converter that uses a charge-domain pipeline.
    Type: Application
    Filed: May 22, 2008
    Publication date: December 4, 2008
    Inventors: T.C.L. Gerhard Sollner, Michael P. Anthony
  • Publication number: 20080042169
    Abstract: A method and structure of providing a doped plug to improve the performance of CCD gaps is discussed. A highly-doped region is implemented in a semiconductor, aligned beneath a gap. The plug provides a highly-conductive region at the semiconductor surface, therefore preventing the development of a region where potential is significantly influenced by surface charges.
    Type: Application
    Filed: May 30, 2007
    Publication date: February 21, 2008
    Inventors: William Washkurak, Michael Anthony, Gerhard Sollner