Abstract: A method and a completely integrable circuit arrangement are proposed for recovery of a timing signal from a data stream. Two groups of phase regulators are supplied with a locally existing reference timing signal, preferably in each case one of mutually complementary reference timing signals. One phase regulator in each case, which has assumed a state within its operating range, is selected to provide the recovered timing signal, while a phase regulator which is currently not selected is kept in the state within its operating range which is diametrically opposite to the state of the currently selected phase regulator. On reaching the limit of the operating range of the currently selected phase regulator, a changeover is made to the phase regulator which has been kept ready until this point.

Abstract: In a broadband signal switching matrix network having a cross-point matrix in FET technology whose switching elements, controlled by a holding memory cell, are each formed with a series circuit of a switching transistor and of an input transistor. Matrix output lines thereof are respectively connected to one terminal of the operating voltage source via a pre-charging transistor that is controlled by a pre-charging clock, that side of the series circuit connected opposite from the matrix output line being permanently connected to the other terminal of the operating voltage source (directly or via a transistor controlled by the output signal and individually associated to the matrix output line) in order to avoid sample clock lines that lead to the switching elements.

Abstract: A crosspoint matrix is constructed in accordance with FET technology and includes matrix input lines which lead to matrix output lines at respective crosspoints, which matrix output lines each comprise, respectively, two signal conductors and having two signal inputs of a differential amplifier to which the two signal conductors of each matrix output line are respectively connectible via a pre-charging transistor to a respective terminal of the operating voltage source, the signal conductors of each matrix output line being respectively connectible to another terminal of the operating voltage source via a respective coupling element that is formed with the series circuit of an input transistor that has its control electrode connected to the sole signal conductor of the appertaining matrix input line and that is further formed by a switching transistor that has its control electrode charged with a through-connect signal or, respectively, an inhibit signal.

Abstract: In a broadband signal switching network with a switching point matrix constructed in FET technology, an input driver circuit is connected for feeding a respective matrix input line, which driver circuit is blocked via an inhibit input when a prescribed signal level is reached on the respective matrix input line which guarantees a safe switch through of the switching element connected with the matrix input line, whereby a further recharging of the matrix input line is prevented.

Abstract: A broadband signal switching equipment constructed in field effect transistor technology has gates at the inputs of the switching point matrix, and output drive circuits having threshold values at the outputs of the switching point matrix. The output signal of a connection, which preferably proceeds via a switching point residing in the center of the switching point matrix and which transmits a fixed signal during each bit through connect interval, is used to block the gates on the input side, given a change of the signal condition of the output signal, whereby a further charge reversal of the switching point matrix output lines is avoided.

Abstract: In a broadband signal switching matrix network having a cross-point matrix in FET technology whose switching elements, each controlled by a holding memory cell, are each formed with a series circuit of a switching transistor and of an input transistor, this series circuit (for a switching element situated in the through-connect state) forms a cross-point-associated, one branch of a differential amplifier whose other branch shared by the cross-points connecting to one and the same matrix output line is formed by an identical or similar transistor series circuit of an output amplifier circuit that is individually associated to the matrix output line. Thus, the matrix output line is connected to one terminal of an operating voltage source via a source transistor.

Abstract: Switch elements having a relatively high forward resistance are provided in a broadband signal switching equipment comprising a crosspoint matrix constructed in FET technology and having input driver circuits and output amplifier circuits. The output amplifier circuits each include a cascade network of a CMOS inverter and a D flip-flop, and a switch having a relatively low forward resistance by which the line leading from the switch element to the inverter input is at least approximately reloaded to the potential corresponding to the switching threshold of the inverter. The switch element is reloaded in a preliminary phase of a bit switching time interval, in order, proceeding from that potential, to be reloaded in the following primary phase to the potential corresponding to the respective bit connected therethrough.

Abstract: Switches having a relatively high forward resistance are provided in a broadband signal switching equipment comprising a crosspoint matrix constructed in field effect transistor technology and provided with input drivers and output amplifiers. The output amplifiers respectively comprise an iterative network of a hysteresis-affected comparator and a D flip-flop, as well as a holding memory and a switch by way of which the holding memory is reloaded in a respective primary phase of a bit switching time interval. The reloading occurs at least approximately to the potential momentarily prevailing on the output line section leading away from the switch, this potential then continuing to be maintained at the second comparator input in the following switching phase.

Abstract: A circuit arrangement for time regeneration of digital signals comprises a correction circuit and a control circuit containing a low-pass filter. For time regeneration of broadband digital signals coded in a DC-free code in broadband digital signal switching and/or transmission systems, a correction element is inserted into the signal path and includes a digital signal input and a control input. The digital signal experiences an increase running time at its signal edges of the one operational sign in the correction element and simultaneously experiences a reduced running time at its signal edges of the other operational sign based on the measure of each DC component occurring in the digital signal. The control circuit comprises a limiter which receives the digital signal and a low-pass filter connected to the limiter and to the control input of the correction element, the control circuit identifying such a DC component.

Abstract: In a broadband signal space switching device comprising a crosspoint matrix constructed in FET technology whose switch elements are respectively controlled by a cross-point-associated memory cell which is decoder-controlled in two coordinate directions, the memory cell is formed by an n-channel transistor and two cross-coupled inverter circuits of which one has its input side connected to the appertaining decoder output of the one selection decoder via an n-channel transistor which, in turn, is charged at its control electrode with the corresponding output signal of the selection decoder, and of which the other leads at its output side to the control input of the appertaining switch element. The switch element is constructed from a single n-channel transistor.

Abstract: For driving an IC module with output digital signals of another IC module, mutually-identical input circuits are provided for the individual digital signals, the respective switching thresholds of the input circuits, controlled by a control circuit shared by the input circuits, being set based on the DC component appearing in a digital signal representative of the remaining digital signals. Positional changes of the digital signals are therefore compensated by positional changes of the switching thresholds.