Patents by Inventor Germaine Troillard

Germaine Troillard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6506655
    Abstract: A method of manufacturing a bipolar transistor in an N-type semiconductor substrate, including the steps of depositing a first base contact polysilicon layer and doping it; depositing a second silicon oxide layer; forming in the first and second layers an opening; annealing to form a third thin oxide layer and harden the second oxide layer; implanting a P-type dopant; depositing a fourth silicon nitride layer; depositing a fifth silicon oxide layer and etching it; anisotropically etching the fifth, fourth, and third layers; performing cleanings during which the fifth layer is reetched and takes a flared profile; depositing a sixth polysilicon layer; and implanting an N-type dopant.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: January 14, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Yvon Gris, Germaine Troillard
  • Publication number: 20020053316
    Abstract: The present invention relates to a method of deposition of a silicon layer on a single-crystal silicon substrate, so that the silicon layer is a single-crystal layer, but of different orientation than the substrate, including the steps of defining a window on the substrate; creating inside the window interstitial defects with an atomic proportion lower than one for one hundred; and performing a silicon deposition in conditions generally corresponding to those of an epitaxial deposition, but at a temperature lower than 850° C.
    Type: Application
    Filed: November 19, 2001
    Publication date: May 9, 2002
    Inventors: Yvon Gris, Germaine Troillard, Jocelyne Mourier
  • Patent number: 6372570
    Abstract: A method of manufacturing a capacitor includes the steps of depositing a first metal level and etching it to leave in place a region corresponding to a first plate of a capacitor and an area of contact with an upper level; depositing an insulating layer; forming a first opening above the first capacitor plate; depositing a thin insulating layer; forming a second opening above the contact area; depositing a second metal level; removing by physico-chemical etching the second metal layer outside regions where it fills up the openings; and depositing a third metal level and leaving in place portions thereof.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: April 16, 2002
    Assignees: STMicroelectronics S. A., Koninkluke Philips Electronics N.V.
    Inventors: Yvon Gris, Germaine Troillard, Jocelyne Mourier, Jos Guelen, Geneviève Lunardi, Henri Banvillet, Jean-Claude Oberlin, Catherine Maddalon
  • Patent number: 6165265
    Abstract: The present invention relates to a method of deposition of a silicon layer on a single-crystal silicon substrate 11 , so that the silicon layer is a single-crystal layer, but of different orientation than the substrate, including the steps of defining a window 13 on the substrate; creating inside the window interstitial defects 14 with an atomic proportion lower than one for one hundred; and performing a silicon deposition 15 in conditions generally corresponding to those of an epitaxial deposition, but at a temperature lower than 750.degree. C.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: December 26, 2000
    Assignee: STMicroelectronics S.A.
    Inventors: Yvon Gris, Germaine Troillard, Jocelyne Mourier
  • Patent number: 5970333
    Abstract: The present invention relates to a method of forming deep trenches in a BICMOS-type integrated circuit wherein the formation of a bipolar transistor includes the steps of depositing a base polysilicon layer, depositing a protection oxide layer, forming an emitter-base opening, and etching the silicon oxide protection layer and the base polysilicon layer outside the bipolar transistor areas. The formation of the trenches includes the steps of opening the protection oxide and base polysilicon layers above a thick oxide region while the emitter-base opening is being made, etching the thick oxide layer while the protection oxide layer is being etched, and etching the silicon under the thick oxide while the base polysilicon is being etched.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: October 19, 1999
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Yvon Gris, Jocelyne Mourier, Germaine Troillard