Abstract: Methods and systems to substantially eliminate effects of EMI burst noise in an Ethernet system are provided herein. The method includes the step of computing and storing filter coefficients configured to adapt to a range of EMI frequencies. The method further comprises the step of receiving a signal and detecting EMI and frequency of the EMI in the received signal. The method further comprises selecting filter coefficients corresponding to the determined frequency of the detected EMI and adjusting a frequency response of one or more filters using the selected filter coefficients so as to substantially eliminate effects of the EMI in the received signal. The method further includes the step of sending filter coefficients to a link partner corresponding to the frequency of the detected EMI.

Abstract: Methods and systems to substantially eliminate effects of EMI burst noise in an Ethernet system are provided herein. The method includes the step of computing and storing filter coefficients configured to adapt to a range of EMI frequencies. The method further comprises the step of receiving a signal and detecting EMI and frequency of the EMI in the received signal. The method further comprises selecting filter coefficients corresponding to the determined frequency of the detected EMI and adjusting a frequency response of one or more filters using the selected filter coefficients so as to substantially eliminate effects of the EMI in the received signal. The method further includes the step of sending filter coefficients to a link partner corresponding to the frequency of the detected EMI.

Abstract: Various embodiments of the present invention provide systems and methods for decoding encoded information. For example, a decoder including a branch metric calculator that conditionally calculates a branch metric based on either an actual input or a saturated input. Such a branch metric calculator is operable to receive an actual input, and to compare the actual input with an expected range. At times, the aforementioned comparison yields a comparison result indicating that the actual input is outside of the expected range. A first branch metric associated with a first branch is calculated. Where the first branch has an expected value representing a boundary of the expected range, calculating the first branch metric is done using the saturated input. Further, a second branch metric associated with a second branch is calculated. Where the second branch has an expected value representing something other than a boundary of the expected range, calculating the second branch metric is done using the actual input.

Abstract: A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.

Abstract: Various embodiments of the present invention provide systems and methods for decoding encoded information. For example, a decoder including a branch metric calculator that conditionally calculates a branch metric based on either an actual input or a saturated input. Such a branch metric calculator is operable to receive an actual input, and to compare the actual input with an expected range. At times, the aforementioned comparison yields a comparison result indicating that the actual input is outside of the expected range. A first branch metric associated with a first branch is calculated. Where the first branch has an expected value representing a boundary of the expected range, calculating the first branch metric is done using the saturated input. Further, a second branch metric associated with a second branch is calculated. Where the second branch has an expected value representing something other than a boundary of the expected range, calculating the second branch metric is done using the actual input.

Abstract: A data detection and decoding system in which a single parity bit added to the end of each code word by the encoder is used in the channel detector to improve the accuracy with which bit decisions are made in the channel detector. The bit estimates and the reliability estimates are then processed by the decoder to recover the original input bits. By using single parity for this dual purpose in combination with a decoder that follows the channel detector and uses the bit estimates and reliability estimates to recover the original input bits, performance of the data detection and decoding system is greatly improved while also overcoming the disadvantages of known digital recording systems.

Abstract: A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.

Abstract: User data is read from a medium having servo data and user data encoded thereon. The user data is read with a read/write head that is operable in a write mode and a read mode. Servo data is read in a time window following a transition from write mode to read mode, with a frequency passband that has a first low frequency corner. User data is read from the medium after expiration of the time window, with a frequency passband that has a second low frequency corner that is lower than the first low frequency corner.

Abstract: A data detection and decoding system in which a single parity bit added to the end of each code word by the encoder is used in the channel detector to improve the accuracy with which bit decisions are made in the channel detector. The bit estimates and the reliability estimates are then processed by the decoder to recover the original input bits. By using single parity for this dual purpose in combination with a decoder that follows the channel detector and uses the bit estimates and reliability estimates to recover the original input bits, performance of the data detection and decoding system is greatly improved while also overcoming the disadvantages of known digital recording systems.

Abstract: User data is read from a medium having servo data and user data encoded thereon. The user data is read with a read/write head that is operable in a write mode and a read mode. Servo data is read in a time window following a transition from write mode to read mode, with a frequency passband that has a first low frequency corner. User data is read from the medium after expiration of the time window, with a frequency passband that has a second low frequency corner that is lower than the first low frequency corner.

Abstract: A timing error recovery system includes a phase locked loop that receives a continuous time input signal, samples the input signal at a sampling rate and generates a voltage control signal. A statistical estimator, such as a maximum a posteriori estimator, compares the voltage control signal with an expected error based upon a statistical model and produces an adjusted voltage control signal that drives a voltage controlled oscillator to adjust the sampling rate.

Abstract: The invention includes disk drive circuitry, systems, and methods. The disk drive system comprises control circuitry and a disk device. The disk device stores data and transfers an analog signal representing the data. The control circuitry receives the analog signal, converts the analog signal into a digital signal, and transfers the digital signal. The control circuitry includes zero forcing circuitry and an adaptive filter. The zero forcing circuitry produces new coefficients for the adaptive filter. The control circuitry may also include an analog-to-digital converter, detector, decoder, and LMS circuitry. The analog-to-digital converter receives and samples the analog signal to generate a sampled signal. The adaptive filter shapes the sampled signal based on coefficients to produce an equalized signal. The detector detects binary data from the equalized signal, and the decoder decodes the binary data to generate the digital signal.