Patents by Inventor Gernot Biese

Gernot Biese has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230170314
    Abstract: A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.
    Type: Application
    Filed: January 13, 2023
    Publication date: June 1, 2023
    Inventors: Jonas Höhenberger, Gernot Biese
  • Patent number: 11587889
    Abstract: A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: February 21, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Jonas Höhenberger, Gernot Biese
  • Publication number: 20210091013
    Abstract: A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 25, 2021
    Inventors: Jonas Höhenberger, Gernot Biese
  • Patent number: 7601549
    Abstract: A method of processing semiconductor wafers comprises forming a pattern of recesses in an exposed surface of each wafer in a lot, prior to an epitaxy step. At least one recessed test structure is included in the pattern of recesses. At least one dimension of the recessed test structure is determined prior to the epitaxy step, then a corresponding dimension of an epitaxial structure grown above the recessed test structure in the epitaxy step is measured. A deviation between the dimension of the recessed test structure and the dimension of the epitaxial structure is determined and, from the deviation, the process temperature at which the epitaxy step was performed is determined. In case the deviation exceeds a predetermined limit, the temperature in the process chamber is adjusted for a subsequent lot of wafers to be processed.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: October 13, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Gernot Biese, Ulrich Clement
  • Publication number: 20080261334
    Abstract: A method of processing semiconductor waters comprises forming a pattern of recesses in an exposed surface of each water in a lot, prior to an epitaxy step. At least one recessed test structure is included in the pattern of recesses. At least one dimension of the recessed test structure is determined prior to the epitaxy step, then a corresponding dimension of an epitaxial structure grown above the recessed test structure in the epitaxy step is measured. A deviation between the dimension of the recessed test structure and the dimension of the epitaxial structure is determined and, from the deviation, the process temperature at which the epitaxy step was performed is determined. In case the deviation exceeds a predetermined limit, the temperature in the process chamber is adjusted for a subsequent lot of waters to be processed.
    Type: Application
    Filed: April 22, 2008
    Publication date: October 23, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gernot Biese, Ulrich Clement
  • Publication number: 20080002171
    Abstract: A method for in-line monitoring a lens controller of a photolithography system in which a plurality of wafers of a lot are processed in succession and which includes a lens for projecting a mask pattern on the wafers and a lens controller for correcting magnification of the lens includes the steps of printing a circuit pattern on each of the wafers of the lot by projecting a mask pattern on the wafers by means of a lens, determining a shot magnification value for a sample of the wafers, and continuously monitoring the variation of the shot magnification values, wherein a variation of the shot magnification values exceeding a first predetermined value indicates a failure of the lens controller.
    Type: Application
    Filed: March 2, 2007
    Publication date: January 3, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Holger Schwekendiek, Gernot Biese, Alexander Urban