Patents by Inventor Gernot Fasching

Gernot Fasching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11923467
    Abstract: A semiconductor device for infrared detection comprises a stack of a first semiconductor layer, a second semiconductor layer and an optical coupling layer. The first semiconductor layer has a first type of conductivity and the second semiconductor layer has a second type of conductivity. The optical coupling layer comprises an optical coupler and at least a first lateral absorber region. The optical coupler is configured to deflect incident light towards the first lateral absorber region. The first lateral absorber region comprises an absorber material with a bandgap Eg in the infrared, IR.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: March 5, 2024
    Assignee: AMS AG
    Inventors: Gerald Meinhardt, Ingrid Jonak-Auer, Gernot Fasching, Bernhard Löffler
  • Publication number: 20230043101
    Abstract: Various embodiments may relate to an optical system. The optical system may include a lens structure configured to generate an outgoing Gaussian beam based on an incoming Gaussian beam. The optical system may also include a light source configured to provide the incoming Gaussian beam to the lens structure. The lens structure may be a flat lens or a phase plate.
    Type: Application
    Filed: January 14, 2021
    Publication date: February 9, 2023
    Inventors: Zhengtong Liu, Jinghua Teng, Hong Son Chu, Qian Wang, Jie Deng, Soo Seng Norman Ang, Xiao Song Eric Tang, Ching Eng Jason Png, Gernot Fasching, Lijian Mai, Anderson Singulani, Jozef Pulko
  • Publication number: 20220244165
    Abstract: A particulate matter sensor module is operable based on sensing light scattered by particulate matter. The sensor includes one or more metalenses, which can help achieve a compact design in some implementations.
    Type: Application
    Filed: June 12, 2020
    Publication date: August 4, 2022
    Inventor: Gernot Fasching
  • Patent number: 10090215
    Abstract: A semiconductor die includes a semiconductor circuit disposed within or over a substrate. A conductive contact pad is disposed over the substrate outside the semiconductor circuit. A floating electrical path ends at a singulated edge of the die. The electrical path is electrically coupled to the conductive contact pad.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: October 2, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Andrew Christopher Graeme Wood, Gernot Fasching, Marius Aurel Bodea, Thomas Krotscheck Ostermann, Erwin Bacher
  • Publication number: 20170125315
    Abstract: A semiconductor die includes a semiconductor circuit disposed within or over a substrate. A conductive contact pad is disposed over the substrate outside the semiconductor circuit. A floating electrical path ends at a singulated edge of the die. The electrical path is electrically coupled to the conductive contact pad.
    Type: Application
    Filed: January 11, 2017
    Publication date: May 4, 2017
    Inventors: Andrew Christopher Graeme Wood, Gernot Fasching, Marius Aurel Bodea, Thomas Krotscheck Ostermann, Erwin Bacher
  • Patent number: 9583406
    Abstract: A method for semiconductor fabrication includes forming a first array of semiconductor circuitry and a second array of semiconductor circuitry separated by a singulation region and a contact region. The method also includes forming a first array of process control monitoring structures within the singulation region of a substrate. The method also includes forming a first array of contact pads disposed in the contact region. The method also includes forming electrical connections between the first array of process control monitoring structures and the first array of contact pads, wherein all external electrical connections to the first array of process control monitoring structures are made through the first array of contact pads.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: February 28, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Andrew Christopher Graeme Wood, Gernot Fasching, Marius Aurel Bodea, Thomas Krotscheck Ostermann, Erwin Bacher
  • Publication number: 20160276233
    Abstract: A method for semiconductor fabrication includes forming a first array of semiconductor circuitry and a second array of semiconductor circuitry separated by a singulation region and a contact region. The method also includes forming a first array of process control monitoring structures within the singulation region of a substrate. The method also includes forming a first array of contact pads disposed in the contact region. The method also includes forming electrical connections between the first array of process control monitoring structures and the first array of contact pads, wherein all external electrical connections to the first array of process control monitoring structures are made through the first array of contact pads.
    Type: Application
    Filed: March 17, 2015
    Publication date: September 22, 2016
    Inventors: Andrew Christopher Graeme Wood, Gernot Fasching, Marius Aurel Bodea, Thomas Krotscheck Ostermann, Erwin Bacher