Abstract: An equalizer for partial response signals is described which is constituted by a shift register and an analog adder, from the output of which a corrected signal is produced. Two of the switching stages forming the shift register have their outputs connected to inputs of an additional analog adder, and one of these shift register stage outputs is connected to the analog adder over an adjustable amplifier. The output of the additional analog adder is connected to a correlator, the value of the output signal of which controls the gain of the adjustable amplifier.

Abstract: Apparatus for controlling the phase of a clock signal in a data transmission system is described. In the latter system the data signal is pulse amplitude modulated, routed to a receiver-demodulator over a transmission path, the data signal retrieved by means of a sampling circuit and coupled to a data sink. A difference signal is produced from the demodulated and the data signals; the amplitudes of the difference signal characterize the amplitude differences between the demodulated and the data signals at predetermined sampling instants. Using the demodulated signal a slope signal, which is indicative of the slope of the demodulated signal at the sampling instants is produced. The difference and slope signals are multiplied producing a product signal having amplitudes equal to the product of the latter two signals. The product signal forms a control signal for altering the phase of the clock signal by adding to or suppressing pulses emitted from a frequency divider.