Abstract: Disclosed is process for maufacture of a type “BC” body contacted SOI transistor with a process for making these transistors in a manufacturing environment to providing a structure which removes overlay tolerance from the effective transistor width during the course of manufacture. The width is determined by RX on the top side, but by PC on the other with source and drain connected together. In the preferred embodiment such a structure is used as the top part of the SOI transistor with the bottom part a mirror image of the top part such that the effect of the PC to RX overlay is reversed, and the top part and bottom part are connected by a common body part. For the bottom part an “UP misalignment will make the device with large, while a “DOWN” misalignment will make the device width smaller. Thus, if PC is misalleged with respect to RX, any width errors introduced in the top part of the transistor will be exactly canceled by the bottom part of the transistor.