Patents by Inventor Geroge Landers

Geroge Landers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030233219
    Abstract: The invention includes combinatorial logic networks emulating ROMs (RECLNs) and an emulation method for ROMs, as well as emulating synchronous ROMs with RECLN's coupled to synchronizing interfaces. The invention includes methods and apparatus generating synthesizable RECLN descriptions, as well as, circuit descriptions, netlists, circuit layouts, mask sets, unpackaged integrated circuit wafers, integrated circuits, and systems products using the synthesizable RECLN descriptions and products derived therefrom. The invention also includes method and apparatus for doing business involving generation of synthesizable RECLN descriptions and/or the above mentioned derived products. The invention also includes creating installation mechanisms for synthesizable RECLN generation methods to create systems generating synthesizable RECLN descriptions.
    Type: Application
    Filed: May 23, 2002
    Publication date: December 18, 2003
    Inventors: Geroge Landers, Earle Willis Jennings