Abstract: The present invention relates to a method for determining an actual junction temperature (Tj) and/or an actual collector current (IC) of an IGBT device, wherein the IGBT device has a main emitter (EM) and an auxiliary emitter (EA), comprising the steps of; measuring the characteristics of an emitter voltage drop (VEE?) as a difference between a main emitter voltage (VE) at the main emitter (EM) and an auxiliary emitter voltage (VE?) at the auxiliary emitter (EA) during a switching operation of the IGBT device; and determining the junction temperature and/or the collector current (IC) based on the characteristics of the emitter voltage drop (VEE?).

Abstract: The present invention relates to a method for determining an actual junction temperature (Tj) and/or an actual collector current (Ic) of an IGBT device, wherein the IGBT device has a main emitter (EM) and an auxiliary emitter (EA), comprising the steps of; measuring the characteristics of an emitter voltage drop (VEE?) as a difference between a main emitter voltage (VE) at the main emitter (EM) and an auxiliary emitter voltage (VE?) at the auxiliary emitter (EA) during a switching operation of the IGBT device; and determining the junction temperature and/or the collector current (IC) based on the characteristics of the emitter voltage drop (VEE?).

Abstract: A system and method are provided for monitoring in real time the operating state of an IGBT device, to determine a junction temperature and/or the remaining lifetime of an IGBT device. The system includes a differential unit configured to receive a gate-emitter voltage characteristic of the IGBT device to be measured and to differentiate the gate-emitter voltage characteristic to obtain pulses correlating with edges formed by a Miller plateau phase during a switch-off phase of the IGBT device. The system also includes a timer unit configured to measure the time delay between the obtained pulses indicating the start and end of the Miller plateau phase during the switch-off phase of the IGBT device, and a junction temperature calculation unit configured to determine at least one of the junction temperature of the IGBT device and/or the remaining lifetime of the IGBT device based on the measured time delay.

Abstract: A controller circuit is specified, having a step-up controller, a resonant converter connected downstream of the step-up controller on the output side, a transformer, a rectifier, which rectifier is connected to the secondary winding of the transformer on the input side, and a CLL resonant circuit connected to the resonant converter and to the primary winding of the transformer, which CLL resonant circuit has a resonance capacitance and a first and a second resonance inductance. In order to reduce the switching losses, the CLL resonant circuit is embodied as a “T” circuit.

Abstract: A controller circuit is specified, having a step-up controller, a resonant converter connected downstream of the step-up controller on the output side, a transformer, a rectifier, which rectifier is connected to the secondary winding of the transformer on the input side, and a CLL resonant circuit connected to the resonant converter and to the primary winding of the transformer, which CLL resonant circuit has a resonance capacitance and a first and a second resonance inductance. In order to reduce the switching losses, the CLL resonant circuit is embodied as a “T” circuit.

Abstract: The document specifies a method for fault handling in a converter circuit for switching three voltage levels, in which the converter circuit has a converter subsystem provided for each phase (R,S,T), in which a top fault current path (A) or a bottom fault current path (B) in the converter subsystem is detected, the top fault current path (A) running through the first, second, third and sixth power semiconductor switches in the converter subsystem or through the first and fifth power semiconductor switches (S1, S5) in the converter subsystem, and the bottom fault current path (B) running through the second, third, fourth and fifth power semiconductor switches in the converter subsystem or through the fourth and sixth power semiconductor switches in the converter subsystem, and in which the power semiconductor switches are switched on the basis of a fault switching sequence.

Abstract: The document specifies a method for fault handling in a converter circuit for switching three voltage levels, in which the converter circuit has a converter subsystem provided for each phase (R,S,T), in which a top fault current path (A) or a bottom fault current path (B) in the converter subsystem is detected, the top fault current path (A) running through the first, second, third and sixth power semiconductor switches in the converter subsystem or through the first and fifth power semiconductor switches (S1, S5) in the converter subsystem, and the bottom fault current path (B) running through the second, third, fourth and fifth power semiconductor switches in the converter subsystem or through the fourth and sixth power semiconductor switches in the converter subsystem, and in which the power semiconductor switches are switched on the basis of a fault switching sequence.

Abstract: A converter circuit with short-circuit current protection having a DC voltage circuit (1) is proposed, which DC voltage circuit (1) is formed by a DC voltage circuit subsystem (2.1), the DC voltage circuit subsystem (2.1) having a first energy store (3) and a second energy store (4), which is connected in series with the first energy store (3), and a fuse (5). Furthermore, the converter circuit has at least one pair of branches (6) provided for each phase (R, S, T) and connected in parallel with the DC voltage circuit (1), each pair of branches (6) having power semiconductor switches. In order to achieve a low-inductance converter circuit, the fuse (5) forms the connection between the first energy store (3) and the second energy store (4).

Abstract: A converter circuit with short-circuit current protection having a DC voltage circuit (1) is proposed, which DC voltage circuit (1) is formed by a DC voltage circuit subsystem (2.1), the DC voltage circuit subsystem (2.1) having a first energy store (3) and a second energy store (4), which is connected in series with the first energy store (3), and a fuse (5). Furthermore, the converter circuit has at least one pair of branches (6) provided for each phase (R, S, T) and connected in parallel with the DC voltage circuit (1), each pair of branches (6) having power semiconductor switches. In order to achieve a low-inductance converter circuit, the fuse (5) forms the connection between the first energy store (3) and the second energy store (4).

Abstract: A short circuit within the dynamic voltage restorer (1) is immediately detected by a short circuit detection units (9) which permanently monitors currents and voltages in the voltage source converter (3) and energy storage capacitor bank (2). Upon detection a fast discharge of the capacitor bank (2) including firing of all available semiconductors of the voltage source converter (3) and distributing the resulting current stress as evenly as possible within the voltage source converter (3) is initiated. Instead of letting costly fuses interrupt the high short circuit currents, these currents are detected and evenly distributed within the converter.

Abstract: A short circuit within the dynamic voltage restorer (1) is immediately detected by a short circuit detection units (9) which permanently monitors currents and voltages in the voltage source converter (3) and energy storage capacitor bank (2). Upon detection a fast discharge of the capacitor bank (2) including firing of all available semiconductors of the voltage source converter (3) and distributing the resulting current stress as evenly as possible within the voltage source converter (3) is initiated. Instead of letting costly fuses interrupt the high short circuit currents, these currents are detected and evenly distributed within the converter.