Patents by Inventor Geroncio G. Galicia

Geroncio G. Galicia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transport processor for processing multiple transport streams
    Patent number: 7149230
    Abstract: A processing apparatus for processing multiple video programs from one or more transport streams. The processing apparatus has a transport processing circuit that includes multiple transport processor units. The transport processor units utilize a common transport processor memory unit having demux context entries containing processing and hardware state information for packet types. Each transport processor unit includes a transport interface for identifying data packets to be acquired from the transport stream, a demultiplexing processor for processing the acquired data packets, and a demultiplexing DMA unit for memory handling operations of the processed data packets. Index chaining allows the transport processor units to access information from the transport processor memory unit. The method uses indices to access demux context entries from the transport processor memory unit. Related DMA indices are used to access memory handling information from the transport processor memory unit.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: December 12, 2006
    Assignee: Microsoft Corporation
    Inventors: Louis F. Coffin, III, Deepak Prakash, James A. Lundblad, Victor A. Tirva, Geroncio G. Galicia, Paul B. Brown, James A. Baldwin
  • Transport processor for processing multiple transport streams
    Publication number: 20030169783
    Abstract: A processing apparatus for processing multiple video programs from one or more transport streams. The processing apparatus has a transport processing circuit that includes multiple transport processor units. The transport processor units utilize a common transport processor memory unit having demux context entries containing processing and hardware state information for packet types. Each transport processor unit includes a transport interface for identifying data packets to be acquired from the transport stream, a demultiplexing processor for processing the acquired data packets, and a demultiplexing DMA unit for memory handling operations ofthe processed data packets. Index chaining allows the transport processor units to access information from the transport processor memory unit. The method uses indices to access demux context entries from the transport processor memory unit. Related DMA indices are used to access memory handling information from the transport processor memory unit.
    Type: Application
    Filed: March 8, 2002
    Publication date: September 11, 2003
    Inventors: Louis F. Coffin, Deepak Prakash, James A. Lundblad, Victor A. Tirva, Geroncio G. Galicia, Paul B. Brown, James A. Baldwin