Abstract: A refreshing organization for use in a main memory with dynamic information storage. In the case of a memory matrix, for example, each row of bit positions is addressed by first sub-address signals, with the result that a refreshing operation is performed for the complete information of the relevant row. Within a row, each bit position is addressed by second sub-address signals. A second memory is provided which includes one word position for each bit row of the main memory. The second memory has a comparatively short memory cycle. During the first half of the "slow" memory cycle, a word of the second memory is addressed by the first sub-address signals and is filled with predetermined information. During the second half of the "slow" memory cycle, a next word of the second memory is addressed during each cycle by the position of an address counter. The stored word which is addressed is then read. The output register is constructed as a counter; the information read is increased by 1 and is written back.

Abstract: A storage configuration comprising a main store, a buffer store having a smaller storage capacity, and an associated address store, comprising an address generator in which successive addresses can be generated for identification of the words of the buffer store. Also provided are means whereby the successive addresses can be taken up in the address locations of the address store, with the result that the buffer store can be addressed as a store having successive addresses by way of the address store.