Patents by Inventor Gerrit J VREMAN

Gerrit J VREMAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11411163
    Abstract: Aspects of the embodiments are directed to systems and devices that include a piezo-electric element comprising a top-side electrode and a bottom-side electrode; a metal contact pad electrically connected to the bottom-side electrode; an electrode electrically connected to the top-side electrode; and an encasement encasing the piezo-electric element. The piezo-electric element can be prepared to include steps and metallization for use in one or more types of packaging.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: Gerrit J. Vreman, Mohamed A. Abdelmoneum, Satoshi Suzuki
  • Publication number: 20200020843
    Abstract: Aspects of the embodiments are directed to systems and devices that include a piezo-electric element comprising a top-side electrode and a bottom-side electrode; a metal contact pad electrically connected to the bottom-side electrode; an electrode electrically connected to the top-side electrode; and an encasement encasing the piezo-electric element. The piezo-electric element can be prepared to include steps and metallization for use in one or more types of packaging.
    Type: Application
    Filed: December 30, 2016
    Publication date: January 16, 2020
    Applicant: Intel Corporation
    Inventors: Gerrit J. Vreman, Mohamed A. Abdelmoneum, Satoshi Suzuki
  • Publication number: 20170287816
    Abstract: A semiconductor package may include an electrically conductive leadframe having a aperture extending from an upper surface of the leadframe to the lower surface of the leadframe. A wirebond die may be attached or affixed to the upper surface of the leadframe in a location that at least partially obstructs the aperture. A flip-chip die may be disposed proximate the bottom surface of the leadframe at least partially in the aperture. The flip-chip die may be physically coupled to the wirebond die, the leadframe, or both. A mold compound that exposes the lands on the leadframe and the solder bumps or balls on the flip-chip die may at least partially encapsulate the semiconductor package.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Applicant: Intel Corporation
    Inventor: GERRIT J. VREMAN
  • Patent number: 9420700
    Abstract: An optical touchscreen assembly may employ a photonic chip packaged with a chip surface at an angle inclined between horizontal and vertical orientations. An inclined paddle sawn flat no-leads (IPSFN) package may be affixed to a cover glass surface along a perimeter of a display. IPSFN packages may incorporate a photo-emitter chip and a photo-detector chip that may be inclined for a desired angle of incidence relative to the cover glass. A CMOS integrated optical transceiver package may include inclined photonic chips and a non-inclined CMOS chip having at least one of a photo-emitter driver, or a photo-detector TIA and/or ADC. A chip package lead frame may include cantilevered paddle tabs amenable to controlled deflection during package assembly. An inclined packaging assembly method may include attaching a chip to a lead frame paddle and form pressing the lead frame to incline the chip to a desired angle before encapsulation.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Gerrit J Vreman, Tom E Pearson, Peter L Chang, Jia-Hung Tseng
  • Publication number: 20160088740
    Abstract: An optical touchscreen assembly may employ a photonic chip packaged with a chip surface at an angle inclined between horizontal and vertical orientations. An inclined paddle sawn flat no-leads (IPSFN) package may be affixed to a cover glass surface along a perimeter of a display. IPSFN packages may incorporate a photo-emitter chip and a photo-detector chip that may be inclined for a desired angle of incidence relative to the cover glass. A CMOS integrated optical transceiver package may include inclined photonic chips and a non-inclined CMOS chip having at least one of a photo-emitter driver, or a photo-detector TIA and/or ADC. A chip package lead frame may include cantilevered paddle tabs amenable to controlled deflection during package assembly. An inclined packaging assembly method may include attaching a chip to a lead frame paddle and form pressing the lead frame to incline the chip to a desired angle before encapsulation.
    Type: Application
    Filed: October 13, 2015
    Publication date: March 24, 2016
    Inventors: Gerrit J. VREMAN, Tom E. PEARSON, Peter L. CHANG, Jia-Hung TSENG
  • Patent number: 9263621
    Abstract: An optical touchscreen assembly may employ a photonic chip packaged with a chip surface at an angle inclined between horizontal and vertical orientations. An inclined paddle sawn flat no-leads (IPSFN) package may be affixed to a cover glass surface along a perimeter of a display. IPSFN packages may incorporate a photo-emitter chip and a photo-detector chip that may be inclined for a desired angle of incidence relative to the cover glass. A CMOS integrated optical transceiver package may include inclined photonic chips and a non-inclined CMOS chip having at least one of a photo-emitter driver, or a photo-detector TIA and/or ADC. A chip package lead frame may include cantilevered paddle tabs amenable to controlled deflection during package assembly. An inclined packaging assembly method may include attaching a chip to a lead frame paddle and form pressing the lead frame to incline the chip to a desired angle before encapsulation.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: February 16, 2016
    Assignee: Intel Corporation
    Inventors: Gerrit J Vreman, Tom E Pearson, Peter L Chang, Jia-Hung Tseng
  • Publication number: 20150185895
    Abstract: An optical touchscreen assembly may employ a photonic chip packaged with a chip surface at an angle inclined between horizontal and vertical orientations. An inclined paddle sawn flat no-leads (IPSFN) package may be affixed to a cover glass surface along a perimeter of a display. IPSFN packages may incorporate a photo-emitter chip and a photo-detector chip that may be inclined for a desired angle of incidence relative to the cover glass. A CMOS integrated optical transceiver package may include inclined photonic chips and a non-inclined CMOS chip having at least one of a photo-emitter driver, or a photo-detector TIA and/or ADC. A chip package lead frame may include cantilevered paddle tabs amenable to controlled deflection during package assembly. An inclined packaging assembly method may include attaching a chip to a lead frame paddle and form pressing the lead frame to incline the chip to a desired angle before encapsulation.
    Type: Application
    Filed: December 26, 2013
    Publication date: July 2, 2015
    Inventors: Gerrit J VREMAN, Tom E PEARSON, Peter L CHANG, Jia-Hung TSENG