Patents by Inventor Gerrit Koch
Gerrit Koch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250028644Abstract: The present disclosure relates to a computer implemented method for verification of a cache memory of a device under test. The method comprises executing a cache verification process configured for accessing via an interface and verifying the cache memory of the device under test. Cache accesses to the cache memory of the device under test by the cache verification process via the interface are monitored. A cache access by the cache verification process via the interface is detected. In response to the detecting of the cache access a target of the detected cache access is determined and the cache memory is modified for providing a pre-defined cache read-out result for the detected cache access. Via the interface the pre-defined cache read-out result is returned to the cache verification process in response to the detected cache access.Type: ApplicationFiled: September 18, 2023Publication date: January 23, 2025Inventors: Yvo Thomas Bernard Mulder, Huiyuan Xing, Gerrit Koch, Ulrike Letz
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Patent number: 11099851Abstract: Examples of techniques for branch prediction for indirect branch instructions are described herein. An aspect includes detecting a first register setting instruction in an instruction pipeline of a processor, wherein the first register setting instruction stores a target instruction address in a first register of the processor. Another aspect includes looking up the first register setting instruction in a first table. Another aspect includes, based on there being a hit for the first register setting instruction in the first table, determining instruction address data corresponding to a first indirect branch instruction that is associated with the first register setting instruction in a first entry in the first table. Another aspect includes updating a branch prediction for the first indirect branch instruction in a branch prediction logic of the processor based on the target instruction address.Type: GrantFiled: October 26, 2018Date of Patent: August 24, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wolfgang Gellerich, Peter M. Held, Gerrit Koch, Martin Schwidefsky
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Patent number: 11099919Abstract: Methods testing a data coherency algorithm via a simulated multi-processor environment are provided, which include implementing: (i) a transactional footprint keeping the address of each cache line used by the processor core, (ii) a reference model operating on and keeping a set of timestamps for a cache line, the set including a construction date representing a global timestamp when new data arrives at a private cache hierarchy and an expiration date representing another global timestamp when a cross-invalidation hits the private cache hierarchy, (iii) a core observed timestamp representing a global timestamp of an oldest construction date of data used before, and (iv) interface events monitoring instruction sequences guaranteed by transactional execution to ensure atomicity of a transaction. Upon detecting a transaction end event and finding a cache line of the transactional footprint having an expiration date older than or equal to a core observed time, an error is reported.Type: GrantFiled: January 6, 2020Date of Patent: August 24, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christian Habermann, Gerrit Koch, Martin Recktenwald, Ralf Winkelmann
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Patent number: 10896118Abstract: Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.Type: GrantFiled: March 29, 2019Date of Patent: January 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ophir Erez, Bodo Hoppe, Divya K. Joshi, Gerrit Koch, Parminder Singh
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Patent number: 10830818Abstract: It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.Type: GrantFiled: September 25, 2017Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Carsten Greiner, Minh Cuong Tran, Gerrit Koch, Joerg Walter
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Patent number: 10823782Abstract: It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.Type: GrantFiled: November 8, 2017Date of Patent: November 3, 2020Assignee: International Business Machines CorporationInventors: Carsten Greiner, Minh Cuong Tran, Gerrit Koch, Joerg Walter
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Patent number: 10684857Abstract: A method includes storing a first address of a first instruction executed by a processor core in a first table, where the first instruction writes a value into a register for utilization in addressing memory. The method stores the first address of the first instruction executed by the processor core in a second table with multiple entries, where a register value loaded into the register is utilized as a second address by a second instruction executed by the processor core to access a main memory. The method determines whether an instruction address associated with an instruction executed by the processor core is present in the second table, where the instruction address is the second address. Responsive to determining the instruction address is present in the second table, the method prefetches data from the main memory, where the register value is utilized as the second address in the main memory.Type: GrantFiled: February 1, 2018Date of Patent: June 16, 2020Assignee: International Business Machines CorporationInventors: Wolfgang Gellerich, Gerrit Koch, Peter M. Held, Martin Schwidefsky
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Patent number: 10678974Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.Type: GrantFiled: October 26, 2017Date of Patent: June 9, 2020Assignee: International Business Machines CorporationInventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
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Publication number: 20200142767Abstract: Methods testing a data coherency algorithm via a simulated multi-processor environment are provided, which include implementing: (i) a transactional footprint keeping the address of each cache line used by the processor core, (ii) a reference model operating on and keeping a set of timestamps for a cache line, the set including a construction date representing a global timestamp when new data arrives at a private cache hierarchy and an expiration date representing another global timestamp when a cross-invalidation hits the private cache hierarchy, (iii) a core observed timestamp representing a global timestamp of an oldest construction date of data used before, and (iv) interface events monitoring instruction sequences guaranteed by transactional execution to ensure atomicity of a transaction. Upon detecting a transaction end event and finding a cache line of the transactional footprint having an expiration date older than or equal to a core observed time, an error is reported.Type: ApplicationFiled: January 6, 2020Publication date: May 7, 2020Inventors: Christian HABERMANN, Gerrit KOCH, Martin RECKTENWALD, Ralf WINKELMANN
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Publication number: 20200133678Abstract: Examples of techniques for branch prediction for indirect branch instructions are described herein. An aspect includes detecting a first register setting instruction in an instruction pipeline of a processor, wherein the first register setting instruction stores a target instruction address in a first register of the processor. Another aspect includes looking up the first register setting instruction in a first table. Another aspect includes, based on there being a hit for the first register setting instruction in the first table, determining instruction address data corresponding to a first indirect branch instruction that is associated with the first register setting instruction in a first entry in the first table. Another aspect includes updating a branch prediction for the first indirect branch instruction in a branch prediction logic of the processor based on the target instruction address.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Inventors: Wolfgang Gellerich, Peter M. Held, Gerrit Koch, Martin Schwidefsky
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Patent number: 10635555Abstract: Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor caches, the graph-based coherency verification tool using trace files as input for verifying memory ordering rules of a given processor architecture for accesses to the caches, wherein nodes in a graph represent memory accesses and edges represent dependencies between them. The verifying includes (i) providing a specification of a test case for a self-checking tool, the test case comprising a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files with the self-checking tool for the graph-based coherency verification tool by producing permutations of trace events, which are defined by the sequence of statements of the test case.Type: GrantFiled: January 5, 2018Date of Patent: April 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas P. Grosser, Gerrit Koch, Ralf Winkelmann
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Patent number: 10572617Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.Type: GrantFiled: October 26, 2017Date of Patent: February 25, 2020Assignee: International Business Machines CorporationInventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
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Patent number: 10558510Abstract: Testing a data coherency algorithm of a multi-processor environment. The testing includes implementing a global time incremented every processor cycle and used for timestamping; implementing a transactional execution flag representing a processor core guaranteeing the atomicity and coherency of the currently executed instructions; implementing a transactional footprint, which keeps the address of each cache line that was used by the processor core; implementing a reference model, which operates on every cache line and keeps a set of timestamps for every cache line; implementing a core observed timestamp representing a global timestamp, which is the oldest construction date of data used before; implementing interface events; and reporting an error whenever a transaction end event is detected and any cache line is found in the transactional footprint with an expiration date that is older than or equal to the core observed time.Type: GrantFiled: January 15, 2018Date of Patent: February 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christian Habermann, Gerrit Koch, Martin Recktenwald, Ralf Winkelmann
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Patent number: 10489296Abstract: Embodiments here relate to managing a cache by exploiting a cache line hierarchy is provided. Managing the cache includes reading cache references of a first task from a cache reference save area of a first task data structure in response to a context switch. Further, managing the cache includes prefetching and restoring cache lines of the first task to the cache based on the cache references. Note that the cache lines can be predetermined from a plurality of cache lines associated with the first task during an extraction operation with respect to the first task and the cache line hierarchy.Type: GrantFiled: September 22, 2016Date of Patent: November 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wolfgang Gellerich, Peter M. Held, Gerrit Koch, Christoph Raisch, Martin Schwidefsky
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Publication number: 20190235872Abstract: A method includes storing a first address of a first instruction executed by a processor core in a first table, where the first instruction writes a value into a register for utilization in addressing memory. The method stores the first address of the first instruction executed by the processor core in a second table with multiple entries, where a register value loaded into the register is utilized as a second address by a second instruction executed by the processor core to access a main memory. The method determines whether an instruction address associated with an instruction executed by the processor core is present in the second table, where the instruction address is the second address. Responsive to determining the instruction address is present in the second table, the method prefetches data from the main memory, where the register value is utilized as the second address in the main memory.Type: ApplicationFiled: February 1, 2018Publication date: August 1, 2019Inventors: Wolfgang Gellerich, Gerrit Koch, Peter M. Held, Martin Schwidefsky
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Publication number: 20190227906Abstract: Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.Type: ApplicationFiled: March 29, 2019Publication date: July 25, 2019Inventors: Ophir Erez, Bodo Hoppe, Divya K. Joshi, Gerrit Koch, Parminder Singh
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Patent number: 10318406Abstract: Verifying architectural compliance of a processor core using processor-sparing functions. A simulation of a model for a register-transfer level design of the processor core is performed. A first state of the model is dumped, when no error exists. An error is injected in the model. A second state of the model is dumped, after the injected error is detected in the simulation. Upon dumping the second state, the model is reset and initialized with the first state. State information of the second state is loaded in the reset and initialized model.Type: GrantFiled: February 23, 2017Date of Patent: June 11, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ophir Erez, Bodo Hoppe, Divya K. Joshi, Gerrit Koch, Parminder Singh
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Patent number: 10282265Abstract: Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor caches, the graph-based coherency verification tool using trace files as input for verifying memory ordering rules of a given processor architecture for accesses to the caches, wherein nodes in a graph represent memory accesses and edges represent dependencies between them. The verifying includes (i) providing a specification of a test case for a self-checking tool, the test case comprising a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files with the self-checking tool for the graph-based coherency verification tool by producing permutations of trace events, which are defined by the sequence of statements of the test case.Type: GrantFiled: November 2, 2015Date of Patent: May 7, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas P. Grosser, Gerrit Koch, Ralf Winkelmann
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Publication number: 20190094300Abstract: It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.Type: ApplicationFiled: November 8, 2017Publication date: March 28, 2019Inventors: Carsten Greiner, Minh Cuong Tran, Gerrit Koch, Joerg Walter
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Publication number: 20190094299Abstract: It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.Type: ApplicationFiled: September 25, 2017Publication date: March 28, 2019Inventors: Carsten Greiner, Minh Cuong Tran, Gerrit Koch, Joerg Walter