Abstract: A stacking spacer for a photovoltaic module frame comprises a main body, extending in a longitudinal direction, a connecting member, extending in the longitudinal direction and protruding from the main body, adapted for being inserted in at least one lateral profile groove of the photovoltaic module frame, and two opposed support members, arranged on respective opposed longitudinal sides of the main body, extending in the longitudinal direction, wherein the two opposed support members have complementary forms, whereby at least two stacking spacers can be securely stacked on top of each other. Photovoltaic module frames and tracking device assemblies may include photovoltaic modules comprising such stacking spacers.

Abstract: Apparatus for the industrial production of photovoltaic concentrator modules, consisting of a module frame, a lens disc, a sensor carrier disc and an electrical line routing arrangement, comprising the following features: a) a mount for the stress-free mounting of a module frame by means of clamping elements on both longitudinal sides and stop elements on both transverse sides, wherein the setting of the clamping elements takes place by means of the displacement and rotation of a switching rod, b) a device for a punctiform application of acrylic and a linear application of silicone onto the bearing surfaces of the module frame, c) a respective device for placing the sensor carrier disc or the lens disc, wherein these discs are transported in a stress-free fashion by means of special suction apparatuses and are emplaced with a centrally starting, predetermined contact pressure, d) a device for measuring the respective disc position and for positioning a sensor carrier disc or a lens disc, e) a device for the f

Abstract: The invention relates to a stacking spacer for a photovoltaic module frame, to a photovoltaic module frame, and to a tracking device assembly for said photovoltaic module frame and stacking spacer. The stacking spacer comprises a main body extending in a longitudinal direction, a connecting member, extending in said longitudinal direction and protruding from said main body, adapted for being inserted at least one lateral profile groove of said photovoltaic module frame and two opposed support members, arranged on respective opposed longitudinal sides of said main body, extending in said longitudinal direction, wherein the two opposed support members have complementary forms, whereby at least two stacking spacers can be securely stacked on top of each other.

Abstract: Apparatus for the industrial production of photovoltaic concentrator modules, consisting of a module frame, a lens disc, a sensor carrier disc and an electrical line routing arrangement, comprising the following features: a) a mount for the stress-free mounting of a module frame by means of clamping elements on both longitudinal sides and stop elements on both transverse sides, wherein the setting of the clamping elements takes place by means of the displacement and rotation of a switching rod, b) a device for a punctiform application of acrylic and a linear application of silicone onto the bearing surfaces of the module frame, c) a respective device for placing the sensor carrier disc or the lens disc, wherein these discs are transported in a stress-free fashion by means of special suction apparatuses and are emplaced with a centrally starting, predetermined contact pressure, d) a device for measuring the respective disc position and for positioning a sensor carrier disc or a lens disc, e) a device for the f

Abstract: A nonconductive plate that is plated-through with an electric pin-and-socket connector in a water vapor diffusion resistant manner as well as its use as back side or side wall of a photovoltaic module is provided. The electric pin-and-socket connector includes a push-through element and a pressing element as well as a sealing element located on the pressing element and made of a material with a low water vapor diffusion rate. By the engagement of the push-through element into a retention element on a second side of the nonconducting plate, the sealing element is pressed against the first side of the plate by the pressing element and thus seals the bore in the plate in a water vapor diffusion resistant manner.

Abstract: A substrate made from silicon has a first region and a second region. Through pores are formed in the first region. Pores that do not traverse the substrate are provided in the second region. The production of the work piece is performed with the aid of electrochemical etching of the pores. The entire surface of the substrate is covered with a mask layer that is structured photolithographically on the rear of the substrate. The bottoms of the pores in the second region are etched clear, preferably using KOH.

Abstract: A DRAM capacitor is described that contains a BaSrTiO3 (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential trough in which electrons can be permanently trapped.

Abstract: A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.

Abstract: A capacitor in a semiconductor configuration on a substrate includes a noble-metal-containing first capacitor electrode which is formed with a plurality of mutually spaced-apart lamellae. The lamellae are oriented substantially parallel to a surface of the substrate and are mechanically and electrically connected to one another on a flank by a support structure. The capacitor furthermore has a capacitor dielectric formed of high-∈ dielectric or ferroelectric material disposed on the first capacitor electrode. The capacitor also has a second capacitor electrode on the capacitor dielectric.

Abstract: A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.

Abstract: A method of fabricating a capacitor structure includes the steps of providing a carrier, forming a supporting structure on a surface of the carrier by providing at least two laminations spaced apart from one another and being disposed essentially parallel to the surface of the carrier and by mechanically connecting the two laminations to the carrier through the use of a connecting element. The method further includes the steps of conformally applying a noble-metal-containing first electrode material to an exposed surface of the carrier and to an exposed surface of the supporting structure, forming a first electrode by structuring the noble-metal-containing first electrode material, conformally applying a capacitor dielectric formed of one of a ferroelectric material and a material with a high dielectric constant on the first electrode; and forming a second electrode on the capacitor dielectric.

Abstract: A DRAM capacitor is described that contains a BaSrTiO3 (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential trough in which electrons can be permanently trapped.

Abstract: A capacitor on a semiconductor configuration is formed with a high-&egr; dielectric or a ferroelectric material. A first noble-metal-containing storage electrode has a plurality of horizontal lamellae connected to one another via a support structure. The support structure is arranged on one or preferably two opposite external flanks of the lamellae. During production, firstly (inter alia by deposition of a sequence of layers with an alternating low and high etching rate) a fin stack negative mold, in particular made from p+-polysilicon, is formed, which is then filled conformally with the electrode material.

Abstract: A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.

Abstract: A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material is produced on top of the first conducting layer and the auxiliary layer. The layer sequence may, in particular, have p+/p− silicon layers or silicon/germanium layers. A layer structure with a base of a capacitor to be produced is formed from the layer sequence. Sides of the layer structure are provided with a conducting supporting structure. An opening is formed inside the layer structure, all the way down to the auxiliary layer and then the auxiliary layer and the layers made of the second material are removed. A free surface of the layers made of the first material and the supporting structure are provided with a capacitor dielectric onto which a counter electrode is applied.

Abstract: A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulating intermediate layer, the semiconductor layer being of a first conductivity type and contains a dopant of the first conductivity type. A temperature treatment of the semiconductor substrate at a predefined diffusion temperature is performed, so that the dopant diffuses partially out of the semiconductor layer through the intermediate layer into the semiconductor substrate and forms there a dopant region of the first conductivity type. The electrical conductivity of the intermediate layer is modified, so that an electrical contact between the semiconductor substrate and the semiconductor layer is produced through the intermediate layer.

Abstract: On a carrier a layer sequence is applied which contains alternatingly layers made of a first conducting material and a second material in which both materials are different from a carrier material. An opening is made in the layer sequence, which is filled with a conducting material so that a central supporting structure is produced. Then the layer sequence is structured corresponding to the dimensions of a capacitor and the layers made of the second material are removed selectively, so that a first capacitor electrode is formed. The layer sequence may have especially p.sup.+ -/p.sup.- silicon layers or silicon/germanium layers. An etch-stop layer can also be incorporated as the lowest or second-lowest layer.

Abstract: A method for fabricating a capacitor for a semiconductor memory configuration. In this case, a selectively etchable material is applied to a conductive support, which is connected to a semiconductor body via a contact hole in an insulator layer, and patterned. A first conductive layer is applied thereon and patterned. A hole is introduced into the first conductive layer, through which hole the selectively etchable material is etched out. A cavity is produced under the first conductive layer in the process. The inner surface of the cavity and the outer surface of the first conductive layer are provided with a dielectric layer, to which a second conductive layer is applied and patterned.

Abstract: For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).