Patents by Inventor Gerrit Leusink
Gerrit Leusink has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240387371Abstract: A semiconductor device including at least one barrier-protected metal feature and related methods of fabrication are described. A method of making a semiconductor device includes forming a barrier layer by steps including providing a metal precursor layer and converting the metal precursor layer into one or more two-dimensional monolayers including at least one chalcogenide. The method also includes causing the barrier layer to be in contact with at least one metal feature in a manner effective to provide the at least one barrier-protected metal feature.Type: ApplicationFiled: March 28, 2024Publication date: November 21, 2024Inventors: Kandabara Tapily, Gerrit Leusink, Robert Clark
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Publication number: 20240363333Abstract: In certain embodiments, a method of microfabrication includes depositing a 2D polymer material over a substrate surface having a first material and a second material such that the 2D polymer adheres to the first material without adhering to the second material. The method further includes depositing a target material over the second material. The 2D material adhered to the first material inhibits deposition of the target material over the first material. The method further includes removing the 2D polymer material.Type: ApplicationFiled: April 28, 2023Publication date: October 31, 2024Inventors: Kandabara Tapily, Robert D. Clark, Gerrit Leusink, Charlotte Cutler, Jeffrey Smith
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Publication number: 20240153781Abstract: Embodiments of methods are provided for thermal dry etching of a ruthenium (Ru) metal layer. In the disclosed embodiments, a substrate containing a Ru metal layer formed thereon is exposed to a gas pulse sequence, while the substrate is held at a relatively high substrate temperature (e.g., a temperature greater than or equal to about 160° C.), to provide thermal etching of the Ru metal layer. As described further herein, the gas pulse sequence may generally include a plurality of gas pulses, which are supplied to the substrate sequentially with substantially no overlap between gas pulses. The gas pulses supplied to the substrate form: (i) volatile reaction products that are vaporized from the Ru surface, and (ii) non-volatile oxide surface layers that are removed from the Ru surface by the next gas pulse, resulting in atomic layer etching (ALE) of the Ru metal layer.Type: ApplicationFiled: October 31, 2023Publication date: May 9, 2024Inventors: Hisashi Higuchi, Kai-Hung Yu, Cory Wajda, Gyanaranjan Pattanaik, Kandabara Tapily, Gerrit Leusink, Robert Clark
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Publication number: 20230260801Abstract: A method of processing a substrate that includes: etching a recess in the substrate using a metal hard mask (MHM) layer as an etch mask, the substrate including a dielectric layer over a conductive layer the includes a first conductive material, a portion of the MHM layer remaining over top surfaces of the dielectric layer after the etching; depositing a sacrificial fill over the substrate to at least partially fill the recess; removing the remaining portion of the MHM layer to expose the top surfaces while protecting the recess with the sacrificial fill; removing the sacrificial fill from the recess after removing the MHM layer, the removing of the sacrificial fill including exposing a portion of the conductive layer; and depositing a second conductive material to fill the recess, the depositing of the second conductive material providing an electrical connection between the conductive layer and the second conductive material.Type: ApplicationFiled: April 12, 2022Publication date: August 17, 2023Inventors: Angelique Raley, Hirokazu Aizawa, Kaoru Maekawa, Katie Lutker-Lee, Gerrit Leusink
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Patent number: 11621190Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.Type: GrantFiled: May 28, 2021Date of Patent: April 4, 2023Assignee: Tokyo Electron LimitedInventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
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Publication number: 20230075263Abstract: A semiconductor package is disclosed. The semiconductor package includes a first substrate including a first interconnect structure and a first bonding layer adjacent the first interconnect structure. The semiconductor package includes a second substrate including a second interconnect structure and a second bonding layer adjacent the second interconnect structure. The first bonding layer and second bonding layer each include a metal oxide.Type: ApplicationFiled: July 13, 2022Publication date: March 9, 2023Applicant: Tokyo Electron LimitedInventors: Soo Doo Chae, Sang Cheol Han, Hojin Kim, Kandabara Tapily, Satohiko Hoshino, Adam Gildea, Gerrit Leusink
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Publication number: 20230051311Abstract: A method of forming a metal superlattice structure includes depositing, on a substrate, a layer of a first metal with face-centered-cubic (fcc) crystal structure. The method further includes depositing a layer of ruthenium (Ru) metal with fcc crystal structure on the layer of the first metal. The layer of the first metal may cause the layer of ruthenium metal to have fcc crystal structure.Type: ApplicationFiled: August 9, 2022Publication date: February 16, 2023Inventors: Hiroaki Niimi, Gerrit Leusink, Hiroki Maehara, Einstein Noel Abarra, Naoki Watanabe
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Publication number: 20230009688Abstract: A method of processing a substrate that includes: loading the substrate in a processing system, the substrate including a metal having a metal surface and a first dielectric material having a dielectric material surface, the metal surface and the dielectric material surface being at the same level; etching the metal to form a recessed metal surface below the dielectric material surface; selectively forming a self-assembled monolayer (SAM) on the recessed metal surface using a spin-on process; and depositing a dielectric film including a second dielectric material on the dielectric material surface.Type: ApplicationFiled: June 30, 2022Publication date: January 12, 2023Inventors: Dina H. Triyoso, Lior Huli, Corey Lemley, Robert D. Clark, Gerrit Leusink
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Patent number: 11170992Abstract: A method of area selective deposition for cap layer formation in advanced semiconductor contacts. The method includes providing a planarized substrate including a first dielectric layer and a first metal layer, oxidizing a surface of the first metal layer to form an oxidized metal layer, and selectively depositing a second dielectric layer on the oxidized metal layer. The selectively depositing the second dielectric layer can include moving the planarized substrate below a gas inlet dispensing a deposition gas during a spatial vapor phase deposition process, where the deposition gas is preferentially exposed to the oxidized metal layer extending above a surface of the first dielectric layer.Type: GrantFiled: April 26, 2019Date of Patent: November 9, 2021Assignee: Tokyo Electron LimitedInventors: Kandabara Tapily, Gerrit Leusink
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Publication number: 20210287936Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.Type: ApplicationFiled: May 28, 2021Publication date: September 16, 2021Inventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
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Patent number: 11024535Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.Type: GrantFiled: October 10, 2019Date of Patent: June 1, 2021Assignee: Tokyo Electron LimitedInventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
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Patent number: 10847424Abstract: A method of forming a nanowire device includes providing a substrate containing nanowires between vertical spacers, selectively depositing a high-k film on the nanowires relative to the vertical spacers, and selectively depositing a metal-containing gate electrode layer on the high-k film relative to the vertical spacers. The method can further include selectively depositing a dielectric material on the vertical spacers prior to selectively depositing the high-k film, where the dielectric material has a lower dielectric constant than the high-k film.Type: GrantFiled: June 21, 2019Date of Patent: November 24, 2020Assignee: Tokyo Electron LimitedInventors: Kandabara Tapily, Jeffrey Smith, Gerrit Leusink
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Publication number: 20200118871Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.Type: ApplicationFiled: October 10, 2019Publication date: April 16, 2020Inventors: Kai-Hung Yu, David O'Meara, Nicholas Joy, Gyanaranjan Pattanaik, Robert Clark, Kandabara Tapily, Takahiro Hakamata, Cory Wajda, Gerrit Leusink
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Publication number: 20190393097Abstract: A method of forming a nanowire device includes providing a substrate containing nanowires between vertical spacers, selectively depositing a high-k film on the nanowires relative to the vertical spacers, and selectively depositing a metal-containing gate electrode layer on the high-k film relative to the vertical spacers. The method can further include selectively depositing a dielectric material on the vertical spacers prior to selectively depositing the high-k film, where the dielectric material has a lower dielectric constant than the high-k film.Type: ApplicationFiled: June 21, 2019Publication date: December 26, 2019Inventors: Kandabara Tapily, Jeffrey Smith, Gerrit Leusink
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Publication number: 20190333763Abstract: A method of area selective deposition for cap layer formation in advanced semiconductor contacts. The method includes providing a planarized substrate including a first dielectric layer and a first metal layer, oxidizing a surface of the first metal layer to form an oxidized metal layer, and selectively depositing a second dielectric layer on the oxidized metal layer. The selectively depositing the second dielectric layer can include moving the planarized substrate below a gas inlet dispensing a deposition gas during a spatial vapor phase deposition process, where the deposition gas is preferentially exposed to the oxidized metal layer extending above a surface of the first dielectric layer.Type: ApplicationFiled: April 26, 2019Publication date: October 31, 2019Inventors: Kandabara Tapily, Gerrit Leusink, Takaaki Tsunomura
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Publication number: 20080003360Abstract: A method for increasing deposition rates of metal layers from metal-carbonyl precursors by mixing a vapor of the metal-carbonyl precursor with CO gas. The method includes providing a substrate in a process chamber of a deposition system, forming a process gas containing a metal-carbonyl precursor vapor and a CO gas, and exposing the substrate to the process gas to deposit a metal layer on the substrate by a thermal chemical vapor deposition process.Type: ApplicationFiled: September 18, 2007Publication date: January 3, 2008Applicants: TOKYO ELECTRON LIMITED, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kenji Suzuki, Emmanuel Guidotti, Gerrit Leusink, Fenton McFeely, Sandra Malhotra
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Publication number: 20070032079Abstract: A method for depositing a Ru metal layer on a patterned substrate from a film precursor vapor delivered from a multi-tray film precursor evaporation system. The method comprises providing a patterned substrate in a process chamber of a deposition system, and forming a process gas containing Ru3(CO)12 precursor vapor and a carrier gas comprising CO gas. The process gas is formed by: providing a solid Ru3(CO)12 precursor in a plurality of spaced trays within a precursor evaporation system, wherein each tray is configured to support the solid precursor and wherein the plurality of spaced trays collectively provide a plurality of surfaces of solid precursor; heating the solid precursor in the plurality of spaced trays in the precursor evaporation system to a temperature greater than about 60° C.Type: ApplicationFiled: September 29, 2006Publication date: February 8, 2007Applicant: Tokyo Electron LimitedInventors: Kenji Suzuki, Emmanuel Guidotti, Gerrit Leusink, Masamichi Hara, Daisuke Kuroiwa
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Publication number: 20060228494Abstract: A method and system for depositing a layer from a vaporized solid precursor. The method includes providing a substrate in a process chamber of a deposition system, forming a precursor vapor by light-induced vaporization of a solid precursor, and exposing the substrate to a process gas containing the precursor vapor to deposit a layer including at least one element from the precursor vapor on the substrate.Type: ApplicationFiled: March 29, 2005Publication date: October 12, 2006Applicant: Tokyo Electron Limited of TBS Broadcast CenterInventor: Gerrit Leusink
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Publication number: 20060228898Abstract: A method for preparing an interfacial layer for a high-k dielectric layer on a substrate. A surface of said substrate is exposed to oxygen radicals formed by ultraviolet (UV) radiation induced dissociation of a first process gas comprising at least one molecular composition comprising oxygen to form an oxide film. The oxide film is exposed to nitrogen radicals formed by plasma induced dissociation of a second process gas comprising at least one molecular composition comprising nitrogen to nitridate the oxide film to form the interfacial layer. A high-k dielectric layer is formed on said interfacial layer.Type: ApplicationFiled: March 30, 2005Publication date: October 12, 2006Inventors: Cory Wajda, Masanobu Igeta, Gerrit Leusink
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Publication number: 20060224008Abstract: A method and system for refurbishing a metal carbonyl precursor. The method includes providing a metal precursor vaporization system containing a metal carbonyl precursor containing un-reacted and partially reacted metal carbonyl precursor, flowing a CO-containing gas through the metal precursor vaporization system to a precursor collection system in fluid communication with the metal precursor vaporization system to transfer the un-reacted metal carbonyl precursor vapor to the precursor collection system, and collecting the transferred metal carbonyl precursor in the precursor collection system. A method is provided for monitoring at least one metal carbonyl precursor parameter to determine a status of the metal carbonyl precursor and the need for refurbishing the metal carbonyl precursor.Type: ApplicationFiled: March 31, 2005Publication date: October 5, 2006Inventors: Kenji Suzuki, Gerrit Leusink, Fenton McFeely