Patents by Inventor Gerrit SCHOER

Gerrit SCHOER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230223473
    Abstract: A silicon chip package structure, in particular a metal-oxide-semiconductor field-effect transistor (MOSFET) and method of manufacture is provided. The disclosure provides improvements to a Chip Silicon Package (CSP) structure by reducing the active area needed to be sacrificed to create a drain area.
    Type: Application
    Filed: January 11, 2023
    Publication date: July 13, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Chinmoy Khaund, Pei Heng Hung, Gerrit Schoer
  • Patent number: 10395970
    Abstract: A method for fabricating a dual trench structure. The method includes providing a wafer comprising a semiconductor layer including a top surface. The method includes providing charge compensation trenches and termination trenches open to the top surface that are formed in a single etch step but with different final shield oxide thicknesses. A first shield oxide layer of a first thickness is formed on the plurality of charge compensation surfaces and the termination trench surface, wherein the first thickness of the first shield oxide layer is sufficient to allow formation of voids through the charge compensation trenches. Poly-silicon is deposited to form the electrodes in the charge compensation trenches. An isolated poly-silicon etch and clean etch is performed in the termination trenches to expose the first shield oxide layer. A second shield oxide layer is deposited on the first shield oxide layer in the termination trenches.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: August 27, 2019
    Assignee: VISHAY-SILICONIX
    Inventors: Maxim Fadel, Gerrit Schoer
  • Publication number: 20150162401
    Abstract: A method for fabricating a dual trench structure. The method includes providing a wafer comprising a semiconductor layer including a top surface. The method includes providing charge compensation trenches and termination trenches open to the top surface that are formed in a single etch step but with different final shield oxide thicknesses. A first shield oxide layer of a first thickness is formed on the plurality of charge compensation surfaces and the termination trench surface, wherein the first thickness of the first shield oxide layer is sufficient to allow formation of voids through the charge compensation trenches. Poly-silicon is deposited to form the electrodes in the charge compensation trenches. An isolated poly-silicon etch and clean etch is performed in the termination trenches to expose the first shield oxide layer. A second shield oxide layer is deposited on the first shield oxide layer in the termination trenches.
    Type: Application
    Filed: December 5, 2013
    Publication date: June 11, 2015
    Applicant: VISHAY-SILICONIX
    Inventors: Maxim FADEL, Gerrit SCHOER