Abstract: A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up.

Abstract: A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up.

Abstract: A method and apparatus for determining a time-out period used for switching between a first operational mode and a second operational mode of a data communications link, comprising detecting a signal used to request switching from the first operational mode to the second operational mode; measuring the duration of the signal; and determining the time-out period in dependence on the measured duration of the signal.

Abstract: The invention relates to multi-phase clock system for receiving a plurality of clock signals (CLKo-n) comprising actual time events (aTE) defining different clock phases, the clock signals all having a same clock frequency but different clock phases, the system further arranged for receiving a reference clock signal (REFCLK) for providing reference time events (rTE) for the plurality of clock signals (CLKo-n), the reference clock signal (REFCLK) having a reference frequency different from the clock frequency, the reference frequency being selected such that each one of the subsequent reference time events (rTE) coincides with a desired time event (dTE) for a single one of the plurality of clock signals (CLKo-n).

Abstract: A method and apparatus for determining a time-out period used for switching between a first operational mode and a second operational mode of a data communications link, comprising detecting a signal used to request switching from the first operational mode to the second operational mode; measuring the duration of the signal; and determining the time-out period in dependence on the measured duration of the signal.

Abstract: A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up.

Abstract: The invention relates to multi-phase clock system for receiving a plurality of clock signals (CLKo-n) comprising actual time events (aTE) defining different clock phases, the clock signals all having a same clock frequency but different clock phases, the system further arranged for receiving a reference clock signal (REFCLK) for providing reference time events (rTE) for the plurality of clock signals (CLKo-n), the reference clock signal (REFCLK) having a reference frequency different from the clock frequency, the reference frequency being selected such that each one of the subsequent reference time events (rTE) coincides with a desired time event (dTE) for a single one of the plurality of clock signals (CLKo-n).

Abstract: A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up.

Abstract: The invention relates to a bus communication system for serialized data transmission comprising: a transmitter, a receiver, and a data line, whereby said transmitter is arranged for transmitting a data signal over said data line; said receiver is arranged for receiving said data signal from said data line, wherein said transmitter is arranged for transmitting an end of transmission signal over said data line after transmission of said data signal is completed; and said receiver is arranged for receiving said end of transmission signal from said data line.

Abstract: Disclosed is a mobile data carrier comprising a data-processing circuit; and a supply unit (1) to apply electric energy to power supply terminals for operating the data-processing circuit from an external energy source and (2) controlling voltage and current at external access points of the data carrier, wherein the supply unit including a voltage-limiting control circuit arranged in parallel to the power supply terminals of the data-processing circuit, and a current control device which, with respect to the supply of energy to the data-processing circuit, is arranged in series with the parallel arrangement of the voltage-limiting control circuit and the data-processing circuit.

Abstract: An electronic circuit comprising an amplifier (AMP) for amplifying a binary input signal (Ui) including an input stage coupled to receive the binary input signal (Ui) comprising means for supplying a DC current to the input stage. The means supplies a current having a first (I1) current value to the input stage during a period of time that is approximately equal to the period of time corresponding to a transition phase from a first binary signal value to a second binary signal value. During the remaining time, the means supplies a current having a second (I2) current value which is smaller than the first (I1) current value. By virtue thereof, the electronic circuit only consumes a significant amount of power during a transition phase from the first binary signal value to the second binary signal value. The amplifier (AMP) can be implemented in all kinds of digital circuits, of which the digital voltage range (the difference between the second and the first binary values) must be increased.

Abstract: An electronic circuit comprising an amplifier (AMP) for amplifying a binary input signal (Ui) including an input stage coupled to receive the binary input signal (Ui) comprising means for supplying a DC current to the input stage. Said means supplies a current having a first (I1) current value to the input stage during a period of time that is approximately equal to the period of time corresponding to a transition phase from a first binary signal value to a second binary signal value. During the remaining time, said means supplies a current having a second (I2) current value which is smaller than the first (I1) current value. By virtue thereof, the electronic circuit only consumes a significant amount of power during a transition phase from the first binary signal value to the second binary signal value. The amplifier (AMP) can be implemented in all kinds of digital circuits, of which the digital voltage range (the difference between the second and the first binary values) must be increased.

Abstract: A serial communication system transfers respective first and second signals via respective parallel signal carriers from a transmitter circuit to a receiver circuit. In synchronization with a clock signal (150), the transmitter circuit (110) serially represents a combination of the clock signal and data bit(s) (160) of a data message as the first and second signals (130, 140). At a data bit boundary, the transmitter circuit effects a transition of the first signal (130) if the data bit to be transmitted has a first value and effects a transition of the second signal (140) if the data bit has a different second value. The receiver circuit (120) recovers the clock signal by detecting and combining signal transitions of the first and second signal, for instance using an XOR function, and recovers the data message from the first and/or the second signal.