Abstract: A system and method form searching an associative memory using input key values and first and second hashing sections. Key values (Kn) can be hashed in the first hashing section (102) to generate first output values H1(Kn) that access a first store (104). The first store or memory portion (104) can include “leaf” pointer entries (106-2) and “chunk pointer” entries (106-3). A leaf pointer entry (106-2) points at data associated with an applied key value. A chunk pointer entry (106-3) includes pointer data. If a chunk pointer entry (106-3) is accessed, the key value (Kn) is hashed in the second hashing section (108) to generate second output values H2(Kn) that access a second store or memory portion (110). Second hashing section (108) hashes key values (Kn) according to selection data SEL stored in a chunk pointer entry (106-3).

Abstract: A microprocessor includes an execution engine, a prediction table cache, and a prefetch controller. The execution engine is adapted to issue a memory request. The memory request includes an identifier corresponding to a row location in an external main memory. The prediction table cache is adapted to store a plurality of entries defining an access history of previously encountered memory requests. The prediction table cache is indexed by the identifier. The prefetch controller is adapted to receive the memory request and generate at least one prefetch candidate based on the memory request and the access history. A method for prefetching data in a microprocessor includes receiving a memory request. The memory request includes an identifier corresponding to a row location in an external main memory. The memory request is compared to an access history of previously encountered memory requests. The access history is indexed by the identifier.

Abstract: Predictive cache memory systems and methods are responsive to cache misses to prefetch a data block from main memory based upon the data block which last followed the memory address which caused the cache miss. In response to an access request to main memory for a first main memory data block, which is caused by a primary cache miss, a second main memory data block is identified which was accessed following a previous access request to the main memory for the first main memory data block. Once identified, the second memory data block is stored in a predictive cache if the second main memory data block is not already stored in the predictive cache. Thus, if the next main memory request is for the second main memory block, as was earlier predicted, the second main memory block is already in the predictive cache and may be accessed rapidly.

Abstract: A photoresist (18) is exposed through a design-independent high resolution reticle (20), producing a high resolution image of exposed resist (18A). Photoresist (18) is exposed for the second time through a design-specific low-resolution reticle (24), exposing selected portions (18D) of previously unexposed resist. The remaining portions (18B) of previously unexposed resist form a design-dependent high resolution image. After development of photoresist (18), its unexposed portions (18B) are removed, producing openings (26) in photoresist (18), that can be transferred to underlying material (36), for example by etching openings in that underlying material (36), thereby transferring the design-dependent high-resolution image to it. Since the design-independent high resolution reticle (20) can be prefabricated ahead of time and used to produce many designs with different functions, the above double-exposure method is suitable for fabricating design-specific high resolution features, e.g.

Abstract: A high precision weighted random pattern generation system generates any desired probability of individual bits within a weighted random bit pattern. The system includes a circular memory having a series of weighting factors stored therein, with each weighting factor representing the desired probability of a bit in the weighted random pattern being binary ONE. The random bits from a random number generator and a weighting factor are combined to form a single weighted random bit. The random bits and weighting factor are combined in a series of interconnected multiplexor gates. Each multiplexor gate has two data inputs, one being a bit from the weighting factor, the other being the output of the preceding multiplexor gate. The random number bit controls the output of the multiplexor. For example, when the control input (random bit) is high, the multiplexor output is the weighting factor bit. When the control input (random bit) is low, the multiplexor output is the output of the preceding multiplexor.

Abstract: A computer system is introduced for curve-solid classification (raycasting) of objects in constructive solid geometry (CSG) modeling to produce image representations of two- or three-dimensional objects. The system carries out curve-solid classifications in parallel and at much higher speed than a general purpose computer. It uses primitive classification processors which compute all of the (curve-line or ray) primitive (basic solid bodies: block, cylinder, etc.) intersections in parallel, combine processors which are connected into a binary tree that duplicates the binary tree defining the CSG solid and computes the set operations (union, intersection and difference), and a host computer.