Abstract: By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

Abstract: By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

Abstract: By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may be avoided or at least significantly reduced in the memory areas, thereby increasing production yield and stability of the memory areas.

Abstract: By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

Abstract: By using a disposable spacer approach for forming drain and source regions prior to an amorphization process for re-crystallizing a semiconductor region in the presence of a stressed spacer layer, possibly in combination with enhanced anneal techniques, such as laser and flash anneal processes, a more efficient strain-generating mechanism may be provided. Furthermore, the spacer for forming the metal silicide may be provided with reduced width, thereby positioning the respective metal silicide regions more closely to the channel region. Consequently, an overall enhanced performance may be obtained on the basis of the above-described techniques.

Abstract: Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and extension regions of a field effect transistor using a symmetric implantation scheme, or to further enhance the effectiveness of asymmetric implantation schemes. The transistor performance may be significantly enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even be completely avoided to further enhance the transistor performance.

Abstract: By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may be avoided or at least significantly reduced in the memory areas, thereby increasing production yield and stability of the memory areas.

Abstract: A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers in the formation of contact vias through an interlayer dielectric formed over the transistors.

Abstract: By using a disposable spacer approach for forming drain and source regions prior to an amorphization process for re-crystallizing a semiconductor region in the presence of a stressed spacer layer, possibly in combination with enhanced anneal techniques, such as laser and flash anneal processes, a more efficient strain-generating mechanism may be provided. Furthermore, the spacer for forming the metal silicide may be provided with reduced width, thereby positioning the respective metal silicide regions more closely to the channel region. Consequently, an overall enhanced performance may be obtained on the basis of the above-described techniques.

Abstract: A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers in the formation of contact vias through an interlayer dielectric formed over the transistors.

Abstract: Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and extension regions of a field effect transistor using a symmetric implantation scheme, or to further enhance the effectiveness of asymmetric implantation schemes. The transistor performance may be significantly enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even be completely avoided to further enhance the transistor performance.

Abstract: A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers in the formation of contact vias through an interlayer dielectric formed over the transistors.

Abstract: A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer that carries the device structure, and a window is formed in the etch stop layer. Further, a dielectric layer is formed upon the etch stop layer that has the window. Then, a first contact hole through the dielectric layer and the window down to the backside semiconductor substrate is simultaneously etched with at least one second contact hole through the dielectric layer down to the device structure. The wafer may be a silicon-on-insulator (SOI) wafer, and the etch stop layer and the dielectric layer may be formed by depositing silicon oxynitride and tetraethyl orthosilicate (TEOS), respectively. The device structure may be a CMOS transistor structure.

Abstract: By providing a test structure including a plurality of test pads, the anisotropic behavior of stress and strain influenced electrical characteristics, such as the electron mobility, may be determined in a highly efficient manner. Moreover, the test pads may enable the detection of stress and strain induced modifications with a spatial resolution in the order of magnitude of individual circuit elements.

Abstract: In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner rounding and thus mechanical stress. Therefore, for a specified type of circuit elements, the characteristics of the corresponding isolation trenches may be tailored to achieve an optimum device performance.

Abstract: In an SOI diode structure, the conventional transistor-like MOS configuration is eliminated by replacing the polysilicon line by a completely dielectric region. This region may be used as an implantation mask to control a dopant gradient of a PN-junction that forms below the dielectric region. Moreover, during the salicide process, the dielectric region prevents the PN-junction from being shorted. Thus, a depletion of the active region caused by the MOS structure may be avoided. Therefore, the functioning of the PN-junction is maintained even for extremely thin semiconductor layers.

Abstract: In a barrier formation process, an adhesion layer of refractory metal is deposited on sidewalls and bottom portions of a trench, and, subsequently, a nitride layer of the refractory metal is formed on the adhesion layer. After forming the nitride layer, the substrate is subjected to a heat treatment in a nitrogen-containing atmosphere to further convert residual refractory metal into nitride, thereby improving the barrier properties of the nitride layer in a subsequent process for filling in a contact metal, such as tungsten.

Abstract: A semiconductor device comprises a field effect transistor and a passive capacitor, wherein the dielectric layer of the capacitor is comprised of a high-k material, whereas the gate insulation layer of the field effect transistor is formed of an ultra thin oxide layer or oxynitride layer so as to provide for superior carrier mobility at the interface between the gate insulation layer and the underlying channel region. Since carrier mobility in the capacitor is not of great importance, the high-k material allows the provision of high capacitance per unit area while featuring a thickness sufficient to effectively reduce leakage current.

Abstract: A substantially ohmic substrate contact may be formed in an SOI semiconductor device by using a conductive material, such as aluminum, for the substrate contact that forms an ohmic contact even at low dopant concentrations, usually encountered in SOI substrates. Moreover, a process sequence is disclosed that allows the formation of the ohmic substrate contact at a high degree of compatibility with conventional dual contact approaches.

Abstract: In an SOI diode structure, the conventional transistor-like MOS configuration is eliminated by replacing the polysilicon line by a completely dielectric region. This region may be used as an implantation mask to control a dopant gradient of a PN-junction that forms below the dielectric region. Moreover, during the salicide process, the dielectric region prevents the PN-junction from being shorted. Thus, a depletion of the active region caused by the MOS structure may be avoided. Therefore, the functioning of the PN-junction is maintained even for extremely thin semiconductor layers.