Abstract: Methods and apparatuses for distributing slice area of objects more uniformly to optimize the build process of additive manufacturing techniques are disclosed. For example, a slice area distribution of a 3D design is calculated. Further, it is determined if the calculated slice area distribution and/or other aspects of the 3D design meets a criteria based on one or more quality metrics. If the calculated slice area distribution and/or other aspects of the 3D design do not meet the criteria, the 3D design is adjusted. The determination and adjustment may be performed iteratively until the calculated slice area distribution and/or other aspects of the 3D meet the criteria.

Abstract: A system and method for modifying features in designs of objects to make them physically capable of being manufactured using additive manufacturing techniques and machines is provided, carrying out the following steps: Determine if one or more surfaces of the object have a surface angle below a threshold angle; designate one or more edges including a first edge, the first edge being between a first surface of the one or more surfaces and a second surface of the one or more surfaces, wherein the first surface has a surface angle below the threshold angle and the second surface has a surface angle equal to or above the threshold angle; and generate one or more additional surfaces along the one or more edges in the design file.

Abstract: A system and method for modifying features in designs of objects to make them physically capable of being manufactured using additive manufacturing techniques and machines is provided.

Abstract: A system and method for modifying features in designs of objects to make them physically capable of being manufactured using additive manufacturing techniques and machines is provided.

Abstract: A system and method for modifying features in designs of objects to make them physically capable of being manufactured using additive manufacturing techniques and machines is provided, carrying out the following steps: Determine if one or more surfaces of the object have a surface angle below a threshold angle; designate one or more edges including a first edge, the first edge being between a first surface of the one or more surfaces and a second surface of the one or more surfaces, wherein the first surface has a surface angle below the threshold angle and the second surface has a surface angle equal to or above the threshold angle; and generate one or more additional surfaces along the one or more edges in the design file.

Abstract: Methods and apparatuses for distributing slice area of objects more uniformly to optimize the build process of additive manufacturing techniques are disclosed. For example, a slice area distribution of a 3D design is calculated. Further, it is determined if the calculated slice area distribution and/or other aspects of the 3D design meets a criteria based on one or more quality metrics. If the calculated slice area distribution and/or other aspects of the 3D design do not meet the criteria, the 3D design is adjusted. The determination and adjustment may be performed iteratively until the calculated slice area distribution and/or other aspects of the 3D meet the criteria.

Abstract: Anchor designs for thin film packages are disclosed that, in a preferred embodiment are a combination of SiGe-filled trenches and Si-oxide-filled spacing. Depending on the release process, additional manufacturing process steps are performed in order to obtain a desired mechanical strength. For aggressive release processes, additional soft sputter etch and a Ti—TiN interlayer in the anchor region may be added. The ratio of the total SiGe—SiGe anchor area to the SiO2—SiGe anchor area determines the mechanical strength of the anchor. If this ratio is larger than 1, the thin film package reaches the MIL-standard requirements.

Abstract: A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed.

Abstract: The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.

Abstract: Anchor designs for thin film packages are disclosed that, in a preferred embodiment are a combination of SiGe-filled trenches and Si-oxide-filled spacing. Depending on the release process, additional manufacturing process steps are performed in order to obtain a desired mechanical strength. For aggressive release processes, additional soft sputter etch and a Ti—TiN interlayer in the anchor region may be added. The ratio of the total SiGe—SiGe anchor area to the SiO2—SiGe anchor area determines the mechanical strength of the anchor. If this ratio is larger than 1, the thin film package reaches the MIL-standard requirements.

Abstract: A method is disclosed for manufacturing a sealed cavity in a microelectronic device, comprising forming a sacrificial layer at least at locations where the cavity is to be provided, depositing a membrane layer over the top of the sacrificial layer, patterning the membrane layer in at least two separate membrane layer blocks, removing the sacrificial layer through the membrane layer, and sealing the cavity by sealing the membrane layer, wherein patterning the membrane layer is performed after removal of the sacrificial layer.

Abstract: A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed.

Abstract: The present disclosure proposes a method for manufacturing in a MEMS device a low-resistance contact between a silicon-germanium layer and a layer contacted by this silicon-germanium layer, such as a CMOS metal layer or another silicon-germanium layer, through an opening in a dielectric layer stack separating both layers. An interlayer is formed in this opening, thereby covering at least the sidewalls of the opening on the exposed surface of the another layer at the bottom of this opening. This interlayer may comprise a TiN layer in contact with the silicon-germanium layer. This interlayer can further comprise a Ti layer in between the TiN layer and the layer to be contacted. In another embodiment this interlayer comprises a TaN layer in contact with the silicon-germanium layer. This interlayer can then further comprise a Ta layer in between the TaN layer and the layer to be contacted.