Patents by Inventor Gert J Leusink

Gert J Leusink has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9607888
    Abstract: Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: March 28, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Kai-Hung Yu, Toshio Hasegawa, Tadahiro Ishizaka, Manabu Oie, Fumitaka Amano, Steven Consiglio, Cory Wajda, Kaoru Maekawa, Gert J. Leusink
  • Publication number: 20150221550
    Abstract: Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.
    Type: Application
    Filed: February 3, 2015
    Publication date: August 6, 2015
    Inventors: Kai-Hung Yu, Toshio Hasegawa, Tadahiro Ishizaka, Manabu Oie, Fumitaka Amano, Steven Consiglio, Cory Wajda, Kaoru Maekawa, Gert J. Leusink
  • Patent number: 7189431
    Abstract: A method for forming a passivated metal layer that preserves the properties and morphology of an underlying metal layer during subsequent exposure to oxygen-containing ambients. The method includes providing a substrate in a process chamber, exposing the substrate to a process gas containing a rhenium-carbonyl precursor to deposit a rhenium metal layer on the substrate in a chemical vapor deposition process, and forming a passivation layer on the rhenium metal layer to thereby inhibit oxygen-induced growth of rhenium-containing nodules on the rhenium metal surface.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: March 13, 2007
    Assignees: Tokyo Electron Limited, International Business Machines Corp.
    Inventors: Hideaki Yamasaki, Kazuhito Nakamura, Yumiko Kawano, Gert J. Leusink, Fenton R. McFeely, Paul Jamison
  • Patent number: 7078341
    Abstract: A method for depositing metal layers on semiconductor substrates by a thermal chemical vapor deposition (TCVD) process. The TCVD process utilizes high flow rate of a dilute process gas containing a metal-carbonyl precursor to deposit a metal layer. In one embodiment of the invention, the metal-carbonyl precursor can be selected from at least one of W(CO)6, Ni(CO)4, Mo(CO)6, Co2(CO)8, Rh4(CO)12, Re2(CO)10, Cr(CO)6, and Ru3(CO)12. In another embodiment of the invention, a method is provided for depositing a W layer from a process gas comprising a W(CO)6 precursor at a substrate temperature of about 410° C. and a chamber pressure of about 200 mTorr.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: July 18, 2006
    Assignees: Tokyo Electron Limited, International Business Machines Corporation
    Inventors: Hideaki Yamasaki, Tsukasa Matsuda, Atsushi Gomi, Tatsuo Hatano, Masahito Sugiura, Yumiko Kawano, Gert J Leusink, Fenton R McFeely, Sandra G. Malhotra
  • Patent number: 7067422
    Abstract: A method for forming a tantalum-containing gate electrode structure by providing a substrate having a high-k dielectric layer thereon in a process chamber and forming a tantalum-containing layer on the high-k dielectric layer in a thermal chemical vapor deposition process by exposing the substrate to a process gas containing TAIMATA (Ta(N(CH3)2)3(NC(C2H5)(CH3)2)) precursor gas. In one embodiment of the invention, the tantalum-containing layer can include a TaSiN layer formed from a process gas containing TAIMATA precursor gas, a silicon containing gas, and optionally a nitrogen-containing gas. In another embodiment of the invention, a TaN layer is formed on the TaSiN layer. The TaN layer can be formed from a process gas containing TAIMATA precursor gas and optionally a nitrogen-containing gas. A computer readable medium executable by a processor to cause a processing system to perform the method and a processing system for forming a tantalum-containing gate electrode structure are also provided.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: June 27, 2006
    Assignees: Tokyo Electron Limited, International Business Machines Corporation
    Inventors: Kazuhito Nakamura, Hideaki Yamasaki, Yumiko Kawano, Gert J. Leusink, Fenton R. McFeely, John J. Yurkas, Vijay Narayanan
  • Patent number: 6989321
    Abstract: A method for depositing metal layers on semiconductor substrates by a thermal chemical vapor deposition (TCVD) process includes introducing a process gas containing a metal carbonyl precursor in a process chamber and depositing a metal layer on a substrate. The TCVD process utilizes a short residence time for the gaseous species in the processing zone above the substrate to form a low-resistivity metal layer. In one embodiment of the invention, the metal carbonyl precursor can be selected from at least one of W(CO)6, Ni(CO)4, Mo(CO)6, Co2(CO)8, Rh4(CO)12, Re2(CO)10, Cr(CO)6, and Ru3(CO)12 precursors. In another embodiment of the invention, a method is provided for depositing low-resistivity W layers at substrate temperatures below about 500° C., by utilizing a residence time less than about 120 msec.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: January 24, 2006
    Assignees: Tokyo Electron Limited, International Business Machines Corporation
    Inventors: Hideaki Yamasaki, Tsukasa Matsuda, Atsushi Gomi, Tatsuo Hatano, Masahito Sugiura, Yumiko Kawano, Gert J Leusink, Fenton R McFeely, Sandra G. Malhotra
  • Patent number: 6924223
    Abstract: A method is provided for forming a metal layer on a substrate using an intermittent precursor gas flow process. The method includes exposing the substrate to a reducing gas while exposing the substrate to pulses of a metal-carbonyl precursor gas. The process is carried out until a metal layer with desired thickness is formed on the substrate. The metal layer can be formed on a substrate, or alternately, the metal layer can be formed on a metal nucleation layer.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: August 2, 2005
    Assignees: Tokyo Electron Limited, International Business Machines Corporation
    Inventors: Hideaki Yamasaki, Tsukasa Matsuda, Atsushi Gomi, Tatsuo Hatano, Mitsuhiro Tachibana, Koumei Matsuzava, Yumiko Kawano, Gert J Leusink, Fenton R McFeely, Sandra G. Malhotra, Andrew H Simon, John J Yurkas