Abstract: A neuro-synaptic processing circuitry for performing neuro-synaptic operations based on synaptic weights and neuron states and comprises i) a data memory for storing the synaptic weights and neuron states; the data memory having a first memory port for loading and storing data from and to the data memory; ii) a plurality of neuron processing elements, NPEs, configurable to execute NPE instructions in parallel according to a single instruction, multiple data, SIMD, instruction set; wherein the NPEs have access to respective portions of the memory port; the SIMD instruction set comprising instructions for loading and storing the synaptic weights and neuron states from and to the memory port, and for performing the neuro-synaptic operations; iii) a general-purpose central processing unit, GP-CPU, configured to execute program code; iv) a loop buffer having a register-based memory; an address calculation unit; and a program counter.