Patents by Inventor Gert Kobernik

Gert Kobernik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7489563
    Abstract: A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: February 10, 2009
    Assignee: Qimonda Flash GmbH & Co. KG
    Inventors: Detlev Richter, Mirko Reissmann, Volker Zipprich-Rasch, Gert Köbernik, Uwe Augustin, Konrad Seidel, Andreas Kux, Hans Heitzer, Daniel-André Löhr, Sören Irmer
  • Publication number: 20080181012
    Abstract: A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Applicant: QIMONDA FLASH GMBH & CO. KG
    Inventors: Detlev Richter, Mirko Reissmann, Volker Zipprich-Rasch, Gert Kobernik, Uwe Augustin, Konrad Seidel, Andreas Kux, Hans Heitzer, Daniel-Andre Lohr, Soren Irmer
  • Patent number: 7167395
    Abstract: A method for determining a reading voltage for reading data out of a non-volatile semiconductor memory, wherein the semiconductor memory comprises a plurality of memory cells grouped in a first memory area and a second memory area. A given number of “0”s are stored into the second memory area, and an equal number of “0”s and “1”s are stored in the memory cells of the first memory area. The memory cells of the first memory area are read using an initial first reading voltage. The first reading voltage is adjusted and the memory cells of the first memory area are re-read until an equal number of “0”s and “1”s are read out of the memory cells of the first memory area, to thereby obtain a final first reading voltage. An initial second reading voltage is determined on the basis of the final first reading voltage. The memory cells of the second memory area are read using the initial second reading voltage.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: January 23, 2007
    Assignee: Infineon Technologies Flash GmbH & Co. KG
    Inventors: Gert Kobernik, Uwe Augustin
  • Publication number: 20070014160
    Abstract: A method for determining a reading voltage for reading data out of a non-volatile semiconductor memory, wherein the semiconductor memory comprises a plurality of memory cells grouped in a first memory area and a second memory area. A given number of “0”s are stored into the second memory area, and an equal number of “0”s and “1”s are stored in the memory cells of the first memory area. The memory cells of the first memory area are read using an initial first reading voltage. The first reading voltage is adjusted and the memory cells of the first memory area are re-read until an equal number of “0”s and “1”s are read out of the memory cells of the first memory area, to thereby obtain a final first reading voltage. An initial second reading voltage is determined on the basis of the final first reading voltage. The memory cells of the second memory area are read using the initial second reading voltage.
    Type: Application
    Filed: July 13, 2005
    Publication date: January 18, 2007
    Applicant: Infineon Technologies Flash GmbH & Co. KG
    Inventors: Gert Kobernik, Uwe Augustin