Abstract: In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining a level for programming or erasing a memory segment is provided, wherein a first level for programming or erasing a memory segment is determined as a function of an initial program/erase level. Furthermore, a first updated level is determined for a subsequent program/erase operation of the memory segment and a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment is determined using the first level, wherein the second level is determined as a function of the first updated level.

Abstract: In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining a level for programming or erasing a memory segment is provided, wherein a first level for programming or erasing a memory segment is determined as a function of an initial program/erase level. Furthermore, a first updated level is determined for a subsequent program/erase operation of the memory segment and a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment is determined using the first level, wherein the second level is determined as a function of the first updated level.

Abstract: A memory device (1) includes a memory array (2). The memory array (2) has at least one memory area (5) that includes a plurality of conductive lines (3) and a plurality of memory cells (4) connected to the conductive lines (3). The conductive lines (3) are arranged at positions (n) within the memory area (5). The memory cells (4) are erasable and are programmable by application of an electrical programming pulse (P) supplied via a respective conductive line (3). The memory device (1) is constructed such that for programming of a memory cell (4) an electrical programming pulse (P) is applied which has a programming pulse profile (PP) depending on the position (n) of a respective conductive line (3) to which the memory cell (4) is connected.

Abstract: A method for conducting programming and erasure of charge-trapped memory devices includes: conducting at least one program/erase cycle of a charge-trapped memory device on the basis of a given threshold voltage of the charge-trapped memory device as a reference point; determining a wear-level of the erasing procedure; shifting the reference point according to a result of the determination of the wear-level; conducting one or more program/erase cycle on the basis of the shifted threshold; and conducting read and verify operations on the basis of the shifted threshold.

Abstract: A method for restoring information stored in a memory cell that has a variable characteristic indicating the stored information, wherein a first state is stored if the characteristic is below a reading threshold or a second state is stored if the characteristic is above the reading threshold. The method includes verifying whether the absolute value of a first difference between the characteristic and the reading threshold is larger than a given first threshold. If the absolute value of the first difference is larger than the given first threshold, the method further includes changing the characteristic so that the absolute value of the first threshold is reduced or that the stored state is altered.

Abstract: A memory device (1) includes a memory array (2). The memory array (2) has at least one memory area (5) that includes a plurality of conductive lines (3) and a plurality of memory cells (4) connected to the conductive lines (3). The conductive lines (3) are arranged at positions (n) within the memory area (5). The memory cells (4) are erasable and are programmable by application of an electrical programming pulse (P) supplied via a respective conductive line (3). The memory device (1) is constructed such that for programming of a memory cell (4) an electrical programming pulse (P) is applied which has a programming pulse profile (PP) depending on the position (n) of a respective conductive line (3) to which the memory cell (4) is connected.