Abstract: In prior-art telecommunication systems a two-wire line carrying digital duplex traffic is tapped by inserting, at a line interruption, two mutually coupled hybrid circuits which convert the two-wire line to a four-wire connection, a traffic stream in one direction being conveyed by two of the four wires and a traffic stream in the other direction being conveyed by the further two of the four wires. A disadvantage for this is that the line has to be interrupted. In the telecommunication system according to the invention the tapping is performed by way of discriminator and echo canceller coupled thereto.

Abstract: An arrangement comprising a controllable clock signal source (1), a decision circuit (8) for determining the polarity of a received biphase signal at two successive sampling instants in a single symbol interval, and a phase detector (35) with a first comparator (16) to compare the polarity samples at the two sampling instants with each other. The phase detector generates a control signal for adjusting the frequency and phase of the adjustable clock signal source (1) in response to the output signal of the first comparator. A second comparator (28) compares polarity samples at the same relative sampling instant in two successive sampling instants with each other. The second comparator (28) inhibits phase detector (35) in response to the output signal of this second detector. In the case of false synchronization, the output of phase detector (35) will continue to present the same signal value, so that automatically an adjustment is made of the instant of correct synchronization.

Abstract: Arrangement for generating pulse code modulation values in a telephone set, comprising a microprocessor which includes a working store, in which the microprocessor and the working store are connected by a data bus and an address bus, further including an output circuit for outputting the pulse code modulation values, an output memory connected thereto for storing the pulse code modulation values to be output, the working store and the output memory being incorporated in a single memory circuit. The arrangement is preferably structured in such a way that it comprises an addressing device for generating, in response to the microprocessor's addressing of a random location of the output memory, an address of an output memory location to be read out.

Abstract: A clock signal is generated by taking two samples in each symbol interval T with a mutual distance of about 1/4 T, shifting the two instants in the symbol interval while keeping a fixed mutual distance between them until a first sampling instant has reached a zero, the second sampling instant then being at a minimum or a maximum, the polarity of the second sample indicating the information content of the biphase signal in this interval. When the first sampling instant has reached the zero, the first sampling instant is moved alternately to the left and right of the zero, and the second sampling instant is retained in its place without jitter.