Abstract: A detection stage of an electronic detection device, for example a pH meter, includes an insulating region that receives an element to be analyzed. The insulating region is positioned on a sensing conductive region. A biasing stage includes an electrically conductive region which is capacitively coupled to the conductive region. The electrically conductive region is formed in an uppermost metallization level along with a further conductive region. That further conductive region is electrically connected to the sensing conductive region by a via passing through an insulating layer which insulates the electrically conductive region from the sensing conductive region.

Abstract: A dual gate ion sensitive field effect transistor (ISFET) includes a first bias voltage node coupled to a back gate of the ISFET and a second bias voltage node coupled to a control gate of the ISFET. A bias voltage generator circuit is configured to generate a back gate voltage having a first magnitude and a first polarity for application to the first bias voltage node. The bias voltage generator circuit is further configured to generate a control gate voltage having a second magnitude and a second polarity for application to the second bias voltage node. The second polarity is opposite the first polarity.

Abstract: A detection stage of an electronic detection device, for example a pH meter, includes an insulating region that receives an element to be analyzed. The insulating region is positioned on a sensing conductive region. A biasing stage includes an electrically conductive region which is capacitively coupled to the conductive region. The electrically conductive region is formed in an uppermost metallization level along with a further conductive region. That further conductive region is electrically connected to the sensing conductive region by a via passing through an insulating layer which insulates the electrically conductive region from the sensing conductive region.

Abstract: A dual gate ion sensitive field effect transistor (ISFET) includes a first bias voltage node coupled to a back gate of the ISFET and a second bias voltage node coupled to a control gate of the ISFET. A bias voltage generator circuit is configured to generate a back gate voltage having a first magnitude and a first polarity for application to the first bias voltage node. The bias voltage generator circuit is further configured to generate a control gate voltage having a second magnitude and a second polarity for application to the second bias voltage node. The second polarity is opposite the first polarity.