Abstract: A transfer chamber for a cluster system includes a first body, a second body attached at one side of the first body, and a cover combined with an upper portion of the first body. The transfer chamber further includes a third body at another side of the first body, wherein the third body has the same shape as the second body.

Abstract: A transfer chamber for a cluster system includes a first body, a second body attached at one side of the first body, and a cover combined with an upper portion of the first body. The transfer chamber further includes a third body at another side of the first body, wherein the third body has the same shape as the second body.

Abstract: A transfer chamber for a cluster system includes a first body, a second body attached at one side of the first body, and a cover combined with an upper portion of the first body. The transfer chamber further includes a third body at another side of the first body, wherein the third body has the same shape as the second body.

Abstract: A cluster device having a dual structure includes: a substrate storage containing a plurality of substrates, the substrate storage having an ATM robot that moves said substrates; a first cluster including a first transfer chamber having a vacuum robot, a plurality of first process chambers connected to the first transfer chamber, and a first load lock chamber connected to both the substrate storage and the first transfer chamber; a second cluster including a second transfer chamber under the first transfer chamber, a plurality of second process chambers connected to the second transfer chamber, each of the plurality of second process chambers positioned between the two first process chambers, and a second load lock chamber connected to both the substrate storage and the second transfer chamber.

Abstract: A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a Cr layer are sequentially deposited on a substrate on which a gate wire is formed. Next, the Cr layer is patterned to form a data line, a source electrode and a drain electrode. The doped amorphous silicon layer and the amorphous silicon layer are patterned at the same time, and the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. Subsequently, a passivation layer is deposited and patterned to form a contact hole. An ITO layer is deposited and patterned to form a pixel electrode. According to the present invention, an oxide layer is prevented by performing a sequential deposition of the four layers in a vacuum state. As a result, the on current of the TFT is increased, and HF cleaning is not necessary because no oxide layer is formed. Therefore, the overall TFT manufacturing process is simplified.

Abstract: A cluster device having a dual structure includes: a substrate storage containing a plurality of substrates, the substrate storage having an ATM robot that moves said substrates; a first cluster including a first transfer chamber having a vacuum robot, a plurality of first process chambers connected to the first transfer chamber, and a first load lock chamber connected to both the substrate storage and the first transfer chamber, a second cluster including a second transfer chamber under the first transfer chamber, a plurality of second process chambers connected to the second transfer chamber, each of the plurality of second process chambers positioned between the two first process chambers, and a second load lock chamber connected to both the substrate storage and the second transfer chamber.

Abstract: A showerhead assembly for used in a manufacturing apparatus for a display substrate is provided in the present invention. The showerhead assembly includes a backing plate having a gas inflow, a showerhead having a plurality of gas injection holes, a plurality of first connectors connecting the showerhead and the backing plate at edge portions thereof, and a plurality of second connectors connecting the showerhead and the backing plate in middle portions thereof.

Abstract: A transfer chamber for a cluster system includes a first body, a second body attached at one side of the first body, and a cover combined with an upper portion of the first body. The transfer chamber further includes a third body at another side of the first body, wherein the third body has the same shape as the second body.

Abstract: A showerhead assembly of an apparatus for manufacturing a semiconductor device includes a backing plate having a gas inlet, a showerhead combined with the backing plate at an end portion thereof, wherein the showerhead has a plurality of holes, and a sub heater equipped at a peripheral portion of the showerhead.

Abstract: A transfer chamber for a cluster system includes a first body, a second body attached at one side of the first body, and a cover combined with an upper portion of the first body. The transfer chamber further includes a third body at another side of the first body, wherein the third body has the same shape as the second body.

Abstract: A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a Cr layer are sequentially deposited on a substrate on which a gate wire is formed. Next, the Cr layer is patterned to form a data line, a source electrode and a drain electrode. The doped amorphous silicon layer and the amorphous silicon layer are patterned at the same time, and the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. Subsequently, a passivation layer is deposited and patterned to form a contact hole. An ITO layer is deposited and patterned to form a pixel electrode. According to the present invention, an oxide layer is prevented by performing a sequential deposition of the four layers in a vacuum state. As a result, the on current of the TFT is increased, and HF cleaning is not necessary because no oxide layer is formed. Therefore, the overall TFT manufacturing process is simplified.

Abstract: A cluster device having a dual structure includes: a substrate storage containing a plurality of substrates, the substrate storage having an ATM robot that moves said substrates; a first cluster including a first transfer chamber having a vacuum robot, a plurality of first process chambers connected to the first transfer chamber, and a first load lock chamber connected to both the substrate storage and the first transfer chamber; a second cluster including a second transfer chamber under the first transfer chamber, a plurality of second process chambers connected to the second transfer chamber, each of the plurality of second process chambers positioned between the two first process chambers, and a second load lock chamber connected to both the substrate storage and the second transfer chamber.

Abstract: A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a Cr layer are sequentially deposited on a substrate on which a gate wire is formed. Next, the Cr layer is patterned to form a data line, a source electrode and a drain electrode. The doped amorphous silicon layer and the amorphous silicon layer are patterned at the same time, and the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. Subsequently, a passivation layer is deposited and patterned to form a contact hole. An ITO layer is deposited and patterned to form a pixel electrode. According to the present invention, an oxide layer is prevented by performing a sequential deposition of the four layers in a vacuum state. As a result, the on current of the TFT is increased, and HF cleaning is not necessary because no oxide layer is formed. Therefore, the overall TFT manufacturing process is simplified.

Abstract: A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a Cr layer are sequentially deposited on a substrate on which a gate wire is formed. Next, the Cr layer is patterned to form a data line, a source electrode and a drain electrode. The doped amorphous silicon layer and the amorphous silicon layer are patterned at the same time, and the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. Subsequently, a passivation layer is deposited and patterned to form a contact hole. An ITO layer is deposited and patterned to form a pixel electrode. According to the present invention, an oxide layer is prevented by performing a sequential deposition of the four layers in a vacuum state. As a result, the on current of the TFT is increased, and HF cleaning is not necessary because no oxide layer is formed. Therefore, the overall TFT manufacturing process is simplified.

Abstract: A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a Cr layer are sequentially deposited on a substrate on which a gate wire is formed. Next, the Cr layer is patterned to form a data line, a source electrode and a drain electrode. The doped amorphous silicon layer and the amorphous silicon layer are patterned at the same time, and the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. Subsequently, a passivation layer is deposited and patterned to form a contact hole. An ITO layer is deposited and patterned to form a pixel electrode. According to the present invention, an oxide layer is prevented by performing a sequential deposition of the four layers in a vacuum state. As a result, the on current of the TFT is increased, and HF cleaning is not necessary because no oxide layer is formed. Therefore, the overall TFT manufacturing process is simplified.

Abstract: A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a Cr layer are sequentially deposited on a substrate on which a gate wire is formed. Next, the Cr layer is patterned to form a data line, a source electrode and a drain electrode. The doped amorphous silicon layer and the amorphous silicon layer are patterned at the same time, and the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. Subsequently, a passivation layer is deposited and patterned to form a contact hole. An ITO layer is deposited and patterned to form a pixel electrode. According to the present invention, an oxide layer is prevented by performing a sequential deposition of the four layers in a vacuum state. As a result, the on current of the TFT is increased, and HF cleaning is not necessary because no oxide layer is formed. Therefore, the overall TFT manufacturing process is simplified.

Abstract: A thin film transistor liquid crystal display exhibits a high field effect mobility to permit a high on-current while maintaining a lower off-current. The LCD-TFT has both a microcrystallized silicon layer and an amorphous silicon layer which together serve as a channel layer. An extrinsic semiconductor layer is formed to be in contact with both the microcrystallized silicon layer and the amorphous silicon layer and source and drain electrodes are formed on the extrinsic semiconductor layer.