Abstract: A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address; and at least one bank area, arranged between the global line block and the data transmission block, each bank area containing plural data I/O blocks located in a side of the data transmission block and plural control blocks located in a side of the global line block.

Abstract: A reference circuit in a ferroelectric memory includes a reference plate line and a reference word line adjacently formed in a first direction in correspondence with a cell block including a plurality of unit cells; a plurality of bit lines connected to the unit cells and formed in a second direction; a plurality of parallelly disposed reference capacitors each having a first electrode connected to the reference plate line and a second electrode connected to a storage node SN of a reference cell; an initializing unit connected to the storage node for initializing a level of the reference cell; and a switching block formed between the bit lines and the storage node in correspondence with the bit lines and controlled by signals applied to the reference word line.

Abstract: A column repair circuit and method of a nonvolatile ferroelectric memory device can include: a memory test logic block capable of generating a redundancy active pulse (RAP) and a corresponding fail input/output (IO) number FION<r> if a column address including a fail bit to be repaired is found during test; a power-up sensor capable of generating a power-up pulse if a stable power source voltage is sensed; a first redundancy control block capable of generating first to fifth control signals ENN, ENP, EQN, CPL, and PREC and a sixth control signal ENW in response to the RAP and the power-up pulse; a counter generating n bit counter bit signal increased by one bit through the RAP to correspond to the number of redundancy bits; a redundancy counter decoding control block capable of generating an activated coding signal ENW<n> in response to the counter bit signal of the counter and the sixth control signal ENW; and a redundancy coding block capable of coding a fail column address in response to the co

Abstract: The present invention discloses a magnetic random access memory comprising MRAM cell groups connected in series in forms of an NAND. The MRAM cell groups comprise magnetic tunnel junctions between word lines and P-N diodes, and memory cells for reading and writing data. In the present invention, the cell size can be reduced by comprising MRAM cell arrays wherein one or more MRAM cells are connected in series in forms of an NAND.