Patents by Inventor Geun-Kyu Choi

Geun-Kyu Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10821572
    Abstract: A method of controlling a chemical mechanical polishing (CMP) process, a temperature control, and a CMP apparatus, the method including measuring actual temperatures of at least two regions in a platen in real time during the CMP process in which a polishing pad attached to the platen polishes a substrate held by a polishing head using slurry and deionized water; receiving the measured actual temperatures of the regions; and individually controlling the actual temperatures of the regions in real time during the CMP process to provide the regions with a predetermined set CMP process temperature.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suk-Hoon Jeong, Sang-Hak Lee, Geun-Kyu Choi, Chang-Sun Hwang, Tae-Young Kwon, Young-Sang Kim, Hyung-Kyu Jin, Jeong-Nam Han
  • Publication number: 20190091828
    Abstract: A method of controlling a chemical mechanical polishing (CMP) process, a temperature control, and a CMP apparatus, the method including measuring actual temperatures of at least two regions in a platen in real time during the CMP process in which a polishing pad attached to the platen polishes a substrate held by a polishing head using slurry and deionized water; receiving the measured actual temperatures of the regions; and individually controlling the actual temperatures of the regions in real time during the CMP process to provide the regions with a predetermined set CMP process temperature.
    Type: Application
    Filed: March 20, 2018
    Publication date: March 28, 2019
    Inventors: Suk-Hoon JEONG, Sang-Hak LEE, Geun-Kyu CHOI, Chang-Sun HWANG, Tae-Young KWON, Young-Sang KIM, Hyung-Kyu JIN, Jeong-Nam HAN
  • Patent number: 9153499
    Abstract: Provided is a semiconductor device including first, second and third source/drain regions. A first conductive plug in contact with the first source/drain regions, having a first width and a first height, and including a first material is provided. An interlayer insulating layer covering the first conductive plug and the substrate is disposed. A second conductive plug vertically penetrating the interlayer insulating layer to be in contact with the second source/drain regions, having a second width and a second height, and including a second material is provided. A third conductive plug vertically penetrating the interlayer insulating layer to be in contact with the third source/drain regions, having a third width and a third height, and including a third material is disposed. The second material includes a noble metal, a noble metal oxide or a perovskite-based conductive oxide.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: October 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-Don Kim, Seung-Hwan Lee, Beom-Seok Kim, Kyu-Ho Cho, Oh-Seong Kwon, Geun-Kyu Choi, Ji-Eun Lim, Yong-Suk Tak
  • Publication number: 20140338600
    Abstract: An exhausting apparatus includes an exhaust pump configured to extract unreacted precursor in a process chamber and vent the unreacted precursor out of the exhaust pump, and a first material supplier configured to supply a first material into the exhaust pump. The first material is adsorbable on an interior surface of the exhaust pump to prevent the unreacted precursor from being adsorbed on the interior surface of the exhaust pump.
    Type: Application
    Filed: April 23, 2014
    Publication date: November 20, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Cheol LEE, Beom-Seok KIM, Suk-JIn CHUNG, Geun-Kyu CHOI
  • Publication number: 20140145306
    Abstract: A plurality of metal patterns are disposed on a substrate. A support structure is provided between the plurality of metal patterns. The support structure has a supporter and a glue layer. Each of the plurality of metal patterns has a greater vertical length than a horizontal length on the substrate when viewed from a cross-sectional view. The supporter has a band gap energy of at least 4.5 eV. The glue layer is in contact with the plurality of metal patterns. The supporter and the glue layer are formed of different materials.
    Type: Application
    Filed: February 3, 2014
    Publication date: May 29, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wan-Don KIM, Beom-Seok KIM, Yong-Suk TAK, Kyu-Ho CHO, Seung-hwan LEE, Oh-Seong KWON, Geun-Kyu CHOI
  • Patent number: 8643075
    Abstract: A plurality of metal patterns are disposed on a substrate. A support structure is provided between the plurality of metal patterns. The support structure has a supporter and a glue layer. Each of the plurality of metal patterns has a greater vertical length than a horizontal length on the substrate when viewed from a cross-sectional view. The supporter has a band gap energy of at least 4.5 eV. The glue layer is in contact with the plurality of metal patterns. The supporter and the glue layer are formed of different materials.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-Don Kim, Beom-Seok Kim, Yong-Suk Tak, Kyu-Ho Cho, Seung-Hwan Lee, Oh-Seong Kwon, Geun-Kyu Choi
  • Publication number: 20120299072
    Abstract: Provided is a semiconductor device including first, second and third source/drain regions. A first conductive plug in contact with the first source/drain regions, having a first width and a first height, and including a first material is provided. An interlayer insulating layer covering the first conductive plug and the substrate is disposed. A second conductive plug vertically penetrating the interlayer insulating layer to be in contact with the second source/drain regions, having a second width and a second height, and including a second material is provided. A third conductive plug vertically penetrating the interlayer insulating layer to be in contact with the third source/drain regions, having a third width and a third height, and including a third material is disposed. The second material includes a noble metal, a noble metal oxide or a perovskite-based conductive oxide.
    Type: Application
    Filed: March 21, 2012
    Publication date: November 29, 2012
    Inventors: WAN-DON KIM, Seung-Hwan Lee, Beom-Seok Kim, Kyu-Ho Cho, Oh-Seong Kwon, Geun-Kyu Choi, Ji-Eun Lim, Yong-Suk Tak
  • Publication number: 20120086014
    Abstract: A plurality of metal patterns are disposed on a substrate. A support structure is provided between the plurality of metal patterns. The support structure has a supporter and a glue layer. Each of the plurality of metal patterns has a greater vertical length than a horizontal length on the substrate when viewed from a cross-sectional view. The supporter has a band gap energy of at least 4.5eV. The glue layer is in contact with the plurality of metal patterns. The supporter and the glue layer are formed of different materials.
    Type: Application
    Filed: July 14, 2011
    Publication date: April 12, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wan-Don Kim, Beom-Seok Kim, Yong-Suk Tak, Kyu-Ho Cho, Seung-Hwan Lee, Oh-Seong Kwon, Geun-Kyu Choi