Abstract: Disclosed is an infrared remote control receiver comprising a photo diode for converting an optical signal to an electrical signal, a semiconductor signal processing device for receiving the electrical from the photo diode, eliminating noise components from the electrical signal output from the photo diode and generating a pulse signal corresponding to a remote control signal transmitted from a remote control transmission device, and a micro computer for receiving the pulse signal from the semiconductor signal processing device and performing a remote control operation instructed by a user of the remote control transmission device by decoding the received pulse signal, wherein the semiconductor signal processing device is fabricated using CMOS devices fabrication processes.

Abstract: Disclosed is an infrared remote control receiver comprising a photo diode for converting an optical signal to an electrical signal, a semiconductor signal processing device for receiving the electrical from the photo diode, eliminating noise components from the electrical signal output from the photo diode and generating a pulse signal corresponding to a remote control signal transmitted from a remote control transmission device, and a micro computer for receiving the pulse signal from the semiconductor signal processing device and performing a remote control operation instructed by a user of the remote control transmission device by decoding the received pulse signal, wherein the semiconductor signal processing device is fabricated using CMOS devices fabrication processes.

Abstract: A gain controller using switched capacitors is provided. The gain controller is operable in a sampling mode or an amplifying mode and controls the gain of an analog input signal. The gain controller includes an operational amplifier, input capacitors, a feedback capacitor, and switches. The operational amplifier controls the gain of the analog input signal and generates an output signal having the controlled gain. The input capacitors are connected to the input side of the operational amplifier in parallel. The feedback capacitor is connected between the input side and the output side of the operational amplifier. The switches connect at least one of the input capacitors to the input signal or a reference voltage, in response to the kinds of operation modes and a predetermined externally applied digital gain control signal.

Abstract: A gain controller using switched capacitors is provided. The gain controller is operable in a sampling mode or an amplifying mode and controls the gain of an analog input signal. The gain controller includes an operational amplifier, input capacitors, a feedback capacitor, and switches. The operational amplifier controls the gain of the analog input signal and generates an output signal having the controlled gain. The input capacitors are connected to the input side of the operational amplifier in parallel. The feedback capacitor is connected between the input side and the output side of the operational amplifier. The switches connect at least one of the input capacitors to the input signal or a reference voltage, in response to the kinds of operation modes and a predetermined externally applied digital gain control signal.

Abstract: A gain controller using switched capacitors is provided. The gain controller is operable in a sampling mode or an amplifying mode and controls the gain of an analog input signal. The gain controller includes an operational amplifier, input capacitors, a feedback capacitor, and switches. The operational amplifier controls the gain of the analog input signal and generates an output signal having the controlled gain. The input capacitors are connected to the input side of the operational amplifier in parallel. The feedback capacitor is connected between the input side and the output side of the operational amplifier. The switches connect at least one of the input capacitors to the input signal or a reference voltage, in response to the kinds of operation modes and a predetermined externally applied digital gain control signal.

Abstract: Disclosed is an energy economized pass-transistor logic having a level restoration circuit (50) free from leakage and a full adder using the same. The logic comprises a functional block (10) having a plurality of n type FETs (M1 . . . M4), for performing at least one logical function of inputs (12, 14, 16, 18) to generate two complementary signals (20, 22), the complementary signals (20, 22) being a weak high level signal and a strong low level signal; and a level restoration block (50) having first and second CMOS inverters (52, 54), for restoring the weak high level signal to a strong or full high level signal and preventing a leakage current flowing through one of the first and the second CMOS inverters (52, 54) where the weak high level is applied.

Abstract: Operational amplifier integrated circuits include a differential input stage, a cascode current mirror, a cascode current source and a preferred bias signal generator which is responsive to a clock signal and is electrically coupled to the differential input stage, the cascode current mirror and the cascode current source. This preferred bias signal generator sequentially enables the cascode current mirror and then the differential input stage in response to a rising edge of the clock signal and disables the cascode current mirror and the cascode current source in response to a falling edge of the clock signal. This sequential enablement of the cascode current mirror before the differential input stage improves the unity gain phase margin characteristics of the circuit and the disablement of the cascode current mirror and the cascode current source in response to the falling edge of the clock signal decreases the power consumption requirements of the circuit.

Abstract: A binary-weighted capacitor array is applicable for use in analog-to-digital or digital-to-analog converters, switched-capacitor filters, etc. A plurality of unit capacitors are arranged in a lateral row. The row is laid out in parallel to a switch array so that each metal interconnect between a unit capacitor and a corresponding switch is of a uniform length. This layout eliminates several limitations commonly found in capacitor arrays, including: top-plate parasitic error due to metal interconnections and metal overlap; ratio error due to oxide thickness gradients; and edge-definition errors.

Abstract: A CMOS output buffer circuit includes a predriving circuit which generates two predriving signals, a main driving circuit which has a plurality of parallel connected pull-up transistors and a plurality of parallel connected pull-down transistors, and a sequential driving circuit which provides sequential pull-up and pull-down driving signals to the pull-up and pull-down transistors, respectively. The main driving circuit generates the output signal according to the sequential pull-up or pull-down driving signals, whereby the output signal is developed step by step into either the power supply potential or the ground potential. In the manner, any spike in the switching current is considerably mitigated, thereby reducing switching noise.