Abstract: A semiconductor device may include a first film and a second film defining parts of a trench, a plug conductive film, a via, and a wiring in the trench. The trench may include a second sub-trench having a second width below a first sub-trench having a first width. The plug conductive film may extend from a first side of the first film to penetrate a bottom face of the trench. An uppermost face of the plug conducive film may be in the trench. The via may include an insulating liner between the plug conductive film and the first film. The uppermost face of the plug conductive film and at least a part of a side wall of the plug conductive film may be in contact with the wiring. An upper face of the insulating liner may be exposed by a bottom face of the second sub-trench.

Abstract: A power voltage generator includes a voltage sensor and a power controller. The voltage sensor is configured to sense a first voltage in a first charge sharing period of a gate clock signal and a second voltage in a second charge sharing period of the gate clock signal. The power breaker is configured to disconnect a power based on the first voltage and the second voltage.

Abstract: A power voltage generator includes a voltage sensor and a power controller. The voltage sensor is configured to sense a first voltage in a first charge sharing period of a gate clock signal and a second voltage in a second charge sharing period of the gate clock signal. The power breaker is configured to disconnect a power based on the first voltage and the second voltage.

Abstract: A display device includes a timing controller which transmits a vertical clock signal having rising edges and falling edges to a gate driver and a gate driver which receives the vertical clock signal, to generate a first gate clock signal and a first inverted gate clock signal in accordance with one of the rising edges and the falling edges of the vertical clock signal, and to generate a second gate clock signal and a second inverted gate clock signal in accordance with a remaining one of the rising edges and the falling edges of the vertical clock signal.

Abstract: A display device includes a timing controller which transmits a vertical clock signal having rising edges and falling edges to a gate driver and a gate driver which receives the vertical clock signal, to generate a first gate clock signal and a first inverted gate clock signal in accordance with one of the rising edges and the falling edges of the vertical clock signal, and to generate a second gate clock signal and a second inverted gate clock signal in accordance with a remaining one of the rising edges and the falling edges of the vertical clock signal.

Abstract: A display panel includes: a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels; a gate driver connected to the plurality of gate lines to apply a gate signal voltage; a data driver connected to the plurality of data lines to apply a data voltage and a negative data voltage; and a gate voltage divider for generating a gate signal voltage including gate-on and gate-off voltages to provided it to the gate driver. The gate voltage divider adjusts the gate-off voltage in accordance with a driving time of the display panel and a temperature of the display panel.