Abstract: A film element for driving a display device and a display device using the same are disclosed. The film element includes a film substrate including wirings and pads connected to the wirings, and an IC chip mounted on the film substrate to be connected to the wirings. The pads on the film substrate are grouped into a plurality of areas having different thermal correction amounts. Pads in a second area are closer to the IC chip than pads in a first area. A length of the first area is set to a length obtained by subtracting a first thermal correction amount from a first reference length. A length of the second area is set to a length obtained by subtracting a second thermal correction amount from a second reference length. The second thermal correction amount is smaller than the first thermal correction amount or has a negative value.

Abstract: A film element for driving a display device and a display device using the same are disclosed. The film element includes a film substrate including wirings and pads connected to the wirings, and an IC chip mounted on the film substrate to be connected to the wirings. The pads on the film substrate are grouped into a plurality of areas having different thermal correction amounts. Pads in a second area are closer to the IC chip than pads in a first area. A length of the first area is set to a length obtained by subtracting a first thermal correction amount from a first reference length. A length of the second area is set to a length obtained by subtracting a second thermal correction amount from a second reference length. The second thermal correction amount is smaller than the first thermal correction amount or has a negative value.

Abstract: A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, and a feedback lock check line connecting a last source drive IC of the N source drive ICs to the timing controller. A swing width of an output voltage of the timing controller increases in proportion to a distance between the timing controller and the N source drive ICs.

Abstract: A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, and a feedback lock check line that connects a last source drive IC of the N source drive ICs to the timing controller.

Abstract: A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, and a feedback lock check line connecting a last source drive IC of the N source drive ICs to the timing controller. A swing width of an output voltage of the timing controller increases in proportion to a distance between the timing controller and the N source drive ICs.

Abstract: A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a timing controller, N source drive integrated circuits (ICs), where N is an integer equal to or greater than 2, N pairs of data bus lines, each of which connects the timing controller to each of the N source drive ICs in a point-to-point manner, a lock check line that connects a first source drive IC of the N source drive ICs to the timing controller and cascade-connects the N source drive ICs to one another, and a feedback lock check line that connects a last source drive IC of the N source drive ICs to the timing controller.