Patents by Inventor Ghanashyam A Bailwal

Ghanashyam A Bailwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Verilog to C++ language translator
    Patent number: 7340727
    Abstract: Method and system for translating Verilog to C++ are provided herein. Aspects of the method for translating may include searching for a Verilog pattern in a Verilog file and substituting the Verilog pattern with a C++ language expression, wherein the C++ language expression is associated with the same functionality as the Verilog pattern. It may be identified whether the Verilog file comprises at least one of a task library, a main driver, and a driver module. If the Verilog file comprises a task library, a Verilog task within the task library may be identified; and the Verilog task may be translated into a C++ function. If the Verilog file comprises a main driver, a C++ interface header may be inserted in the Verilog file.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: March 4, 2008
    Assignee: Broadcom Corporation
    Inventor: Ghanashyam A Bailwal
  • Verilog to C++ language translator
    Publication number: 20050166165
    Abstract: Method and system for translating Verilog to C++ are provided herein. Aspects of the method for translating may include searching for a Verilog pattern in a Verilog file and substituting the Verilog pattern with a C++ language expression, wherein the C++ language expression is associated with the same functionality as the Verilog pattern. It may be identified whether the Verilog file comprises at least one of a task library, a main driver, and a driver module. If the Verilog file comprises a task library, a Verilog task within the task library may be identified; and the Verilog task may be translated into a C++ function. If the Verilog file comprises a main driver, a C++ interface header may be inserted in the Verilog file.
    Type: Application
    Filed: January 27, 2004
    Publication date: July 28, 2005
    Inventor: Ghanashyam Bailwal