Patents by Inventor Ghasem PASANDI

Ghasem PASANDI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Efficient pipelined architecture for superconducting single flux quantum logic circuits utilizing dual clocks
    Patent number: 11303281
    Abstract: An SFQ circuit system includes at least one SFQ block having a plurality of SFQ logic gates. Characteristically, at least a portion of the SFQ logic gates are arranged in series. The SFQ circuit system includes a timing system configured to provide a first set of inputs and collect a first set of outputs of the at least one SFQ block at a rate defined by a slow clock frequency while the SFQ logic gates are clocked at a fast clock frequency. Advantageously, the rate is sufficiently slow to allow the first set of inputs to propagate through all levels of the SFQ logic gates to produce the first set of outputs of the at least one SFQ block without colliding with a second set of inputs to the at least one SFQ block.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: April 12, 2022
    Assignee: University of Southern California
    Inventors: Ghasem Pasandi, Massoud Pedram
  • EFFICIENT PIPELINED ARCHITECTURE FOR SUPERCONDUCTING SINGLE FLUX QUANTUM LOGIC CIRCUITS UTILIZING DUAL CLOCKS
    Publication number: 20220021391
    Abstract: An SFQ circuit system includes at least one SFQ block having a plurality of SFQ logic gates. Characteristically, at least a portion of the SFQ logic gates are arranged in series. The SFQ circuit system includes a timing system configured to provide a first set of inputs and collect a first set of outputs of the at least one SFQ block at a rate defined by a slow clock frequency while the SFQ logic gates are clocked at a fast clock frequency. Advantageously, the rate is sufficiently slow to allow the first set of inputs to propagate through all levels of the SFQ logic gates to produce the first set of outputs of the at least one SFQ block without colliding with a second set of inputs to the at least one SFQ block.
    Type: Application
    Filed: April 5, 2021
    Publication date: January 20, 2022
    Inventors: Ghasem PASANDI, Massoud PEDRAM