Abstract: The disclosure relates to a network interface controller for dynamically managing a retransmission delay of a message to resend the message if the retransmission delay is exceeded. The controller includes a communication module to receive an instruction for transmitting a message, said instruction including characteristic data of the message; transmission buffer memory to store the characteristic data and to associate it with a retransmission delay; a slowdown defining calculator to define a value of the division factor from said characteristic data; a reference clock to generate a fixed frequency signal; a frequency divider to generate a reduced frequency signal from the value of the division factor and the fixed frequency signal; and a reduced frequency clock associated with the transmission buffer memory to allow the retransmission delay to be timed from the reduced frequency signal and to trigger a retransmission of the message if the retransmission delay is exceeded.

Abstract: A computer implemented method for processing machine instructions by a physical processor, includes receiving a machine instruction, stored in a memory, to execute, the machine instruction including an identification of at least one first operation to execute and a conditional prefix representing a condition to verify to execute the at least one first operation; evaluating, using a management module, the prefix, and executing, using a processing unit, the at least one first operation identified in the machine instruction, according to whether the condition is verified or not.

Abstract: The disclosure relates to a network interface controller for dynamically managing a retransmission delay of a message to resend the message if the retransmission delay is exceeded. The controller includes a communication module to receive an instruction for transmitting a message, said instruction including characteristic data of the message; transmission buffer memory to store the characteristic data and to associate it with a retransmission delay; a slowdown defining calculator to define a value of the division factor from said characteristic data; a reference clock to generate a fixed frequency signal; a frequency divider to generate a reduced frequency signal from the value of the division factor and the fixed frequency signal; and a reduced frequency clock associated with the transmission buffer memory to allow the retransmission delay to be timed from the reduced frequency signal and to trigger a retransmission of the message if the retransmission delay is exceeded.

Abstract: Managing the end-to-end reliability in the delivery with acknowledgment of data from a source node (10) to a group of destination nodes (21-23), including the steps of marking messages (1) transmitted from the source node (10); upon transmission of a message, incrementation of an overall sequence number; identification of the overall sequence number of a message transmitted by which the source node has not received an acknowledgment; and calculation of the difference between the overall sequence number of the next message to be transmitted and the identified overall sequence number. If the calculated difference is equal to a predefined threshold, suspend the transmission of messages from the source node (10) to the group of destination nodes (21-23) and conclude the presence of an error in the delivery of data.

Abstract: A method of accessing data in a multiprocessor system, wherein the system includes a plurality of processors, with each processor being associated with a respective cache memory, a cache memory management module, a main memory and a main memory management module, the method including: receiving by the cache memory management module an initial request for access to data by a processor; first transmitting by the cache memory management module a first request with respect to the data to at least one cache memory; second transmitting in parallel to the first transmitting by the cache memory management module, a second request with respect to the data to the main memory management module; checking by the main memory management module, whether to initiate querying of the main memory or not, and querying or not by the main memory management module, of the main memory in accordance with the said checking.

Abstract: Managing the end-to-end reliability in the delivery with acknowledgment of data from a source node (10) to a group of destination nodes (21-23), including the steps of marking messages (1) transmitted from the source node (10); upon transmission of a message, incrementation of an overall sequence number; identification of the overall sequence number of a message transmitted by which the source node has not received an acknowledgment; and calculation of the difference between the overall sequence number of the next message to be transmitted and the identified overall sequence number. If the calculated difference is equal to a predefined threshold, suspend the transmission of messages from the source node (10) to the group of destination nodes (21-23) and conclude the presence of an error in the delivery of data.

Abstract: A device for searching for element correspondence in a list, the device including: a plurality of content-addressable memory modules configured so as to be able to compare in parallel an input element with the content thereof, the list being represented by the concatenation of the valid content of the memories in an order defined by a list of priority, a module for the determination, in the list of priority, of the first module wherein the input element corresponds to an element stored in the module, and a module for reading the first element of the determined module corresponding to the input element,

Abstract: A method of accessing data in a multiprocessor system, wherein the system includes a plurality of processors, with each processor being associated with a respective cache memory, a cache memory management module, a main memory and a main memory management module, the method including: receiving by the cache memory management module an initial request for access to data by a processor; first transmitting by the cache memory management module a first request with respect to the data to at least one cache memory; second transmitting in parallel to the first transmitting by the cache memory management module, a second request with respect to the data to the main memory management module; checking by the main memory management module, whether to initiate querying of the main memory or not, and querying or not by the main memory management module, of the main memory in accordance with the said checking.

Abstract: A computer implemented method for processing machine instructions by a physical processor, includes receiving a machine instruction, stored in a memory, to execute, the machine instruction including an identification of at least one first operation to execute and a conditional prefix representing a condition to verify to execute the at least one first operation; evaluating, using a management module, the prefix, and executing, using a processing unit, the at least one first operation identified in the machine instruction, according to whether the condition is verified or not.

Abstract: An information processing system includes processors grouped in nodes (1) associated with one another by links (4) in a variable number of nodes up to the maximum configuration, which is divided into subsets (3) having a critical size relative to a rate of messages between nodes, the nodes in one subset being connected to one another by double serial links, and the nodes of two adjacent subsets being connected by single serial links, the nodes preferably being grouped in two supernodes including two subsets (3).