Abstract: CMOS-compatible high-speed and low power random number generator and techniques for use thereof are provided. In one aspect, a random number generator includes: a noise amplification unit configured to generate an amplified noise signal, wherein the noise amplification unit includes noise amplification unit transistors having a threshold voltage (Vt,amp) of about 0; and a computing unit configured to process the amplified noise signal from the noise amplification unit to generate a stream of random numbers, wherein the computing unit comprises computing unit transistors having absolute values of a Vt,compute that are larger than the Vt,amp of the noise amplification unit transistors in the noise amplification unit. For digital implementations, an analog-to-digital converter configured to digitize the amplified noise signal can be employed. For analog implementations, a sample and hold circuit configured to sample the amplified noise signal can be employed.

Abstract: A semiconductor structure includes a first processor on a first die of a substrate. There is a second processor on a second die of the substrate. There is a one-time programmable (OTP) memory programming circuit, outside of the first and second die, and shared by the first and second processors. Each of the first and second processors include a one-time programmable (OTP) memory. The OTP memory programming circuit is configured to program each OTP memory.

Abstract: CMOS-compatible high-speed and low power random number generator and techniques for use thereof are provided. In one aspect, a random number generator includes: a noise amplification unit configured to generate an amplified noise signal, wherein the noise amplification unit includes noise amplification unit transistors having a threshold voltage (Vt,amp) of about 0; and a computing unit configured to process the amplified noise signal from the noise amplification unit to generate a stream of random numbers, wherein the computing unit comprises computing unit transistors having absolute values of a Vt,compute that are larger than the Vt,amp of the noise amplification unit transistors in the noise amplification unit. For digital implementations, an analog-to-digital converter configured to digitize the amplified noise signal can be employed. For analog implementations, a sample and hold circuit configured to sample the amplified noise signal can be employed.

Abstract: Monolithic, lateral series photovoltaic and photodiode devices on an insulating substrate are provided. In one aspect, a method of forming a photovoltaic device includes: forming a photovoltaic stack on an insulating substrate that includes: a bottom contact layer disposed on the insulating substrate, a BSF layer disposed on the bottom contact layer, a junction layer disposed on the BSF layer, a window layer disposed on the junction layer, and a top contact layer disposed on the window layer; patterning the top contact layer, the window layer, the junction layer, the BSF layer and the bottom contact layer into individual device stacks; forming contact pads on patterned portions of the bottom/top contact layers in each of the device stacks; and forming interconnects in contact with the contact pads that serially connect the device stacks. A photovoltaic device is also provided.

Abstract: A semiconductor structure includes a first processor on a first die of a substrate. There is a second processor on a second die of the substrate. There is a one-time programmable (OTP) memory programming circuit, outside of the first and second die, and shared by the first and second processors. Each of the first and second processors include a one-time programmable (OTP) memory. The OTP memory programming circuit is configured to program each OTP memory.

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

Abstract: A method of forming a thin film transistor (TFT) that includes forming a low temperature polysilicon semiconductor layer on a substrate; and implanting first dopant regions on opposing sides of a channel region of the low temperature polysilicon semiconductor layer. The method may further include epitaxially forming second dopant regions on the first dopant regions. The concentration of the conductivity type dopant in the second dopant regions is greater than a concentration of the conductivity type dopant in the first dopant region. The second dopant regions are formed using a low temperature epitaxial deposition process at a temperature less than 350° C.

Abstract: Embodiments are directed to an integrated circuit for a low-power random number generator that uses a thin-film transistor. Embodiments of the integrated circuit include one or more front-end devices formed on a substrate, and one or more interlayer dielectric (ILD) layers formed on the one or more front-end devices. Embodiments of the integrated circuit also include one or more back-end devices formed on the one or more ILD layers, wherein the one or more back-end devices are configured to amplify a noise signal and transmit an amplified noise signal to the one or more front-end devices for processing.

Abstract: Embodiments are directed to an integrated circuit for a low-power random number generator that uses a thin-film transistor. Embodiments of the integrated circuit include one or more front-end devices formed on a substrate, and one or more interlayer dielectric (ILD) layers formed on the one or more front-end devices. Embodiments of the integrated circuit also include one or more back-end devices formed on the one or more ILD layers, wherein the one or more back-end devices are configured to amplify a noise signal and transmit an amplified noise signal to the one or more front-end devices for processing.

Abstract: A method of forming a thin film transistor (TFT) that includes forming a low temperature polysilicon semiconductor layer on a substrate; and implanting first dopant regions on opposing sides of a channel region of the low temperature polysilicon semiconductor layer. The method may further include epitaxially forming second dopant regions on the first dopant regions. The concentration of the conductivity type dopant in the second dopant regions is greater than a concentration of the conductivity type dopant in the first dopant region. The second dopant regions are formed using a low temperature epitaxial deposition process at a temperature less than 350° C.

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

Abstract: A method of forming a thin film transistor (TFT) that includes forming a low temperature polysilicon semiconductor layer on a substrate; and implanting first dopant regions on opposing sides of a channel region of the low temperature polysilicon semiconductor layer. The method may further include epitaxially forming second dopant regions on the first dopant regions. The concentration of the conductivity type dopant in the second dopant regions is greater than a concentration of the conductivity type dopant in the first dopant region. The second dopant regions are formed using a low temperature epitaxial deposition process at a temperature less than 350° C.

Abstract: A tool for use in forming molded articles, comprising a tool body formed of a ceramic material preferably porous with a porosity of between 40% and 60% and in the form of a foam. The tool body is profiled to define the mold surface(s) of the tool. The outer surface of the tool can be sealed with epoxy sealant to provide the mold surface(s) of the tool. An elastomeric layer can be applied to the surface(s) of the tool body and a resinous material, such as a fiber reinforced material, applied to the elastomeric layer, wherein the elastomeric layer inhibits the movement of resin from the resinous layer into the porous ceramic body, and the resinous layer defines the mold surface.

Abstract: Ion-sensitive field-effect transistors including channel regions of inorganic semiconductor material and organic gate junctions are provided for detecting biological materials or reactions within an electrolyte. The transistors may include self-assembled monolayers to passivate a surface of the inorganic semiconductor material. Bio-sensing material is immobilized by the self-assembled monolayers for use in bio-detection. A back-gate electrode is optionally employed.

Abstract: A heterojunction III-V photovoltaic (PV) cell includes a base layer comprising a III-V substrate, the base layer being less than about 20 microns thick; an intrinsic layer located on the base layer; an amorphous silicon layer located on the intrinsic layer; and a transparent conducting oxide layer located on the amorphous silicon layer.

Abstract: An autonomous integrated circuit (IC) includes a solar cell formed on a bottom substrate of a silicon-on-insulator (SOI) substrate as a handle substrate; an insulating layer of the SOI substrate located on top of the solar cell; and a device layer formed on a top semiconductor layer of the SOI substrate located on top of the insulating layer, wherein a top contact of the device layer is electrically connected to a bottom contact of the solar cell such that the solar cell is enabled to power the device layer.

Abstract: An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination of which is accompanied with appropriate etch.

Abstract: A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each second spacer is adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers.

Abstract: A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.

Abstract: A heterojunction III-V photovoltaic (PV) cell includes a base layer comprising a III-V substrate, the base layer being less than about 20 microns thick; an intrinsic layer located on the base layer; an amorphous silicon layer located on the intrinsic layer; and a transparent conducting oxide layer located on the amorphous silicon layer.