Patents by Inventor Gheorghe Almasi
Gheorghe Almasi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160062771Abstract: There are provided a system, a method and a computer program product for selecting an active data stream (a lane) while running SPMD (Single Program Multiple Data) code on SIMD (Single Instruction Multiple Data) machine. The machine runs an instruction stream over input data streams. The machine increments lane depth counters of all active lanes upon the thread-PC reaching a branch operation. The machine updates the lane-PC of each active lane according to targets of the branch operation. The machine selects an active lane and activates only lanes whose lane-PCs match the thread-PC. The machine decrements the lane depth counters of the selected active lanes and updates the lane-PC of each active lane upon the instruction stream reaching a first instruction. The machine assigns the lane-PC of a lane with a largest lane depth counter value to the thread-PC and activates all lanes whose lane-PCs match the thread-PC.Type: ApplicationFiled: August 26, 2014Publication date: March 3, 2016Applicant: International Business Machines CorporationInventors: Gheorghe Almasi, Jose Moreira, Jessica H. Tseng, Peng Wu
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Publication number: 20140372724Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.Type: ApplicationFiled: June 13, 2013Publication date: December 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gheorghe Almasi, Barnaby Dalton, Ilie G. Tanase, Ettore Tiotto
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Publication number: 20140372725Abstract: Allocating distributed data structures and managing allocation of a symmetric heap can include defining, using a processor, the symmetric heap. The symmetric heap includes a symmetric partition for each process of a partitioned global address space (PGAS) system. Each symmetric partition of the symmetric heap begins at a same starting virtual memory address and has a same global symmetric break. One process of a plurality of processes of the PGAS system is configured as an allocator process that controls allocation of blocks of memory for each symmetric partition of the symmetric heap. Using the processor executing the allocator process, isomorphic fragmentation among the symmetric partitions of the symmetric heap is maintained.Type: ApplicationFiled: June 14, 2013Publication date: December 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gheorghe Almasi, Barnaby Dalton, Ilie G. Tanase, Ettore Tiotto
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Patent number: 7984450Abstract: Methods, apparatus, and products are disclosed for dispatching packets on a global combining network of a parallel computer comprising a plurality of nodes connected for data communications using the network capable of performing collective operations and point to point operations that include: receiving, by an origin system messaging module on an origin node from an origin application messaging module on the origin node, a storage identifier and an operation identifier, the storage identifier specifying storage containing an application message for transmission to a target node, and the operation identifier specifying a message passing operation; packetizing, by the origin system messaging module, the application message into network packets for transmission to the target node, each network packet specifying the operation identifier and an operation type for the message passing operation specified by the operation identifier; and transmitting, by the origin system messaging module, the network packets to theType: GrantFiled: November 28, 2007Date of Patent: July 19, 2011Assignee: International Business Machines CorporationInventors: Gheorghe Almasi, Charles J. Archer
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Patent number: 7984448Abstract: A system and method for supporting collective communications on a plurality of processors that use different parallel programming paradigms, in one aspect, may comprise a schedule defining one or more tasks in a collective operation, an executor that executes the task, a multisend module to perform one or more data transfer functions associated with the tasks, and a connection manager that controls one or more connections and identifies an available connection. The multisend module uses the available connection in performing the one or more data transfer functions. A plurality of processors that use different parallel programming paradigms can use a common implementation of the schedule module, the executor module, the connection manager and the multisend module via a language adaptor specific to a parallel programming paradigm implemented on a processor.Type: GrantFiled: June 26, 2007Date of Patent: July 19, 2011Assignee: International Business Machines CorporationInventors: Gheorghe Almasi, Gabor Dozsa, Sameer Kumar
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Patent number: 7827385Abstract: A parallel computer comprises a plurality of compute nodes organized into at least one operational group for collective parallel operations. Each compute node is assigned a unique rank and is coupled for data communications through a global combining network. One compute node is assigned to be a logical root. A send buffer and a receive buffer is configured. Each element of a contribution of the logical root in the send buffer is contributed. One or more zeros corresponding to a size of the element are injected. An allreduce operation with a bitwise OR using the element and the injected zeros is performed. And the result for the allreduce operation is determined and stored in each receive buffer.Type: GrantFiled: August 2, 2007Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Gheorghe Almasi, Charles J. Archer, Joseph D. Ratterman, Brian E. Smith
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Patent number: 7716407Abstract: Executing application function calls in response to an interrupt including creating a thread; receiving an interrupt having an interrupt type; determining whether a value of a semaphore represents that interrupts are disabled; if the value of the semaphore represents that interrupts are not disabled: calling, by the thread, one or more preconfigured functions in dependence upon the interrupt type of the interrupt; yielding the thread; and if the value of the semaphore represents that interrupts are disabled: setting the value of the semaphore to represent to a kernel that interrupts are hard-disabled; and hard-disabling interrupts at the kernel.Type: GrantFiled: January 3, 2008Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Gheorghe Almasi, Charles J. Archer, Mark E. Giampapa, Thomas M. Gooding, Philip Heidelberger, Jeffrey J. Parker
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Publication number: 20090177828Abstract: Executing application function calls in response to an interrupt including creating a thread; receiving an interrupt having an interrupt type; determining whether a value of a semaphore represents that interrupts are disabled; if the value of the semaphore represents that interrupts are not disabled: calling, by the thread, one or more preconfigured functions in dependence upon the interrupt type of the interrupt; yielding the thread; and if the value of the semaphore represents that interrupts are disabled: setting the value of the semaphore to represent to a kernel that interrupts are hard-disabled; and hard-disabling interrupts at the kernel.Type: ApplicationFiled: January 3, 2008Publication date: July 9, 2009Inventors: Gheorghe Almasi, Charles J. Archer, Mark E. Giampapa, Thomas M. Gooding, Philip Heidelberger, Jeffrey J. Parker
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Publication number: 20090138892Abstract: Methods, apparatus, and products are disclosed for dispatching packets on a global combining network of a parallel computer comprising a plurality of nodes connected for data communications using the network capable of performing collective operations and point to point operations that include: receiving, by an origin system messaging module on an origin node from an origin application messaging module on the origin node, a storage identifier and an operation identifier, the storage identifier specifying storage containing an application message for transmission to a target node, and the operation identifier specifying a message passing operation; packetizing, by the origin system messaging module, the application message into network packets for transmission to the target node, each network packet specifying the operation identifier and an operation type for the message passing operation specified by the operation identifier; and transmitting, by the origin system messaging module, the network packets to theType: ApplicationFiled: November 28, 2007Publication date: May 28, 2009Inventors: Gheorghe Almasi, Charles J. Archer
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Publication number: 20090113308Abstract: Methods, apparatus, and products are disclosed for creating and administering communications schedules for data communications among compute nodes in a data communications network of a parallel computer that include: receiving a communications schedule specifying data communications steps in a message passing operation performed by the compute nodes in the data communications network of the parallel computer; parsing the communications schedule to identify the data communications steps; and generating a graphical representation of the communications schedule, including graphing the data communications steps for the message passing operation.Type: ApplicationFiled: October 26, 2007Publication date: April 30, 2009Inventors: Gheorghe Almasi, Charles J. Archer, Charles C. Erway, Brian E. Smith
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Publication number: 20090037511Abstract: Methods, parallel computers, and computer program products are disclosed for effecting a broadcast with an allreduce operation on a parallel computer, the parallel computer comprising a plurality of compute nodes, the compute nodes organized into at least one operational group of compute nodes for collective parallel operations of the parallel computer, each compute node in the operational group assigned a unique rank, the compute nodes of the operational group coupled for data communications through a global combining network; and one compute node assigned to be a logical root.Type: ApplicationFiled: August 2, 2007Publication date: February 5, 2009Inventors: Gheorghe Almasi, Charles J. Archer, Joseph D. Ratterman, Brian E. Smith
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Publication number: 20090006810Abstract: A system and method for supporting collective communications on a plurality of processors that use different parallel programming paradigms, in one aspect, may comprise a schedule defining one or more tasks in a collective operation an executor that executes the task, a multisend module to perform one or more data transfer functions associated with the tasks, and a connection manager that controls one or more connections and identifies an available connection. The multisend module uses the available connection in performing the one or more data transfer functions. A plurality of processors that use different parallel programming paradigms can use a common implementation of the schedule module, the executor module, the connection manager and the multisend module via a language adaptor specific to a parallel programming paradigm implemented on a processor.Type: ApplicationFiled: June 26, 2007Publication date: January 1, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gheorghe Almasi, Gabor Dozsa, Sameer Kumar
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Patent number: 7383490Abstract: Methods and apparatus perform fault isolation in multiple node computing systems using commutative error detection values for—example, checksums—to identify and to isolate faulty nodes. When information associated with a reproducible portion of a computer program is injected into a network by a node, a commutative error detection value is calculated. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values associated with the node and stores them in memory. When the computer program is executed again by the multiple node computer system, new commutative error detection values are created and stored in memory. The node fault detection apparatus identifies faulty nodes by comparing commutative error detection values associated with reproducible portions of the application program generated by a particular node from different runs of the application program. Differences in values indicate a possible faulty node.Type: GrantFiled: April 14, 2005Date of Patent: June 3, 2008Assignee: International Business Machines CorporationInventors: Gheorghe Almasi, Matthias Augustin Blumrich, Dong Chen, Paul Coteus, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Dirk I. Hoenicke, Sarabjeet Singh, Burkhard D. Steinmacher-Burow, Todd Takken, Pavlos Vranas
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Publication number: 20060248370Abstract: The present invention concerns methods and apparatus for performing fault isolation in multiple node computing systems using commutative error detection values—for example, checksums—to identify and to isolate faulty nodes. In the present invention nodes forming the multiple node computing system are networked together and during program execution communicate with one another by transmitting information through the network. When information associated with a reproducible portion of a computer program is injected into the network by a node, a commutative error detection value is calculated and stored in commutative error detection apparatus associated with the node. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values saved in the commutative error detection apparatus associated with the node and stores them in memory.Type: ApplicationFiled: April 14, 2005Publication date: November 2, 2006Inventors: Gheorghe Almasi, Matthias Blumrich, Dong Chen, Paul Coteus, Alan Gara, Mark Giampapa, Philip Heidelberger, Dirk Hoenicke, Sarabjeet Singh, Burkhard Steinmacher-Burow, Todd Takken, Pavlos Vranas