Abstract: A graphics display adapter has a row interpolator circuit connected to receive the source pixel data synchronized at a first clock rate and to interpolate groups of pixels of row at a second clock rate. A row interpolated storage device receives and retains interpolated source pixel data of each row at the second clock rate. A column interpolator circuit extracts the interpolated source pixel data at a third clock rate. The column interpolator circuit then interpolates groupings of the interpolated source pixel data at the third clock rate and transmits the destination graphic pixel data for display. The second clock rate maybe equal to the first clock rate or the faster of the first and third clock rates.

Abstract: The method and circuit provide an effective implementation to handle the data transferring problem between multiple clock domains. A shift circuit shifts the incoming data stream and a sampling module sequentially samples and outputs each signal in the first group signals and the second group signals by the N sampling pulses with a sequence.

Abstract: A graphics display adapter has a row interpolator circuit connected to receive the source pixel data synchronized at a first clock rate and to interpolate groups of pixels of row at a second clock rate. A row interpolated storage device receives and retains interpolated source pixel data of each row at the second clock rate. A column interpolator circuit extracts the interpolated source pixel data at a third clock rate. The column interpolator circuit then interpolates groupings of the interpolated source pixel data at the third clock rate and transmits the destination graphic pixel data for display. The second clock rate maybe equal to the first clock rate or the faster of the first and third clock rates.

Abstract: A simultaneous read and write memory is shown. The memory is configured into a plurality of sections. Connected to each section is a wordline multiplexer which is used to select a wordline for reading or writing. A write wordline decoder and a read wordline decoder are each connected to all the wordline multiplexers. The multiplexers choose either a write wordline or a read wordline independently for each memory section. A write data path and a read data path are separately connected to each of the memory sections. With the separate write and read wordline addressing and the separate data paths for reading and writing, one section can be written simultaneous to the reading from a second section.

Abstract: A programmable burst sequence counter is described. The counter is capable of counting sequences of binary numbers in a linear burst sequence or interleaved burst sequence starting from a initial binary number that is presented to the inputs of the counter. The programmable burst sequence counter is applicable to the generation of addresses for the storage and retrieval of digital data from memory arrays.